Register Summary: General-Purpose Timer 1; Register Details: General-Purpose Timer 1 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: GENERAL-PURPOSE TIMER 1

Table 228. Timer 1 Register Summary
Address
0x40000400
0x40000404
0x40000408
0x4000040C
0x40000410
0x4000041C

REGISTER DETAILS: GENERAL-PURPOSE TIMER 1

16-Bit Load Value Register
Address: 0x40000400, Reset: 0x0000, Name: T1LD
Table 229. Bit Descriptions for T1LD
Bits Bit Name
[15:0] LOAD
16-Bit Timer Value Register
Address: 0x40000404, Reset: 0x0000, Name: T1VAL
Table 230. Bit Descriptions for T1VAL
Bits Bit Name
[15:0] VAL
Control Register
Address: 0x40000408, Reset: 0x000A, Name: T1CON
Table 231. Bit Descriptions for T1CON
Bits Bit Name
[15:13] RESERVED
12 EVENTEN
[11:8] EVENT
7 RLD
[6:5] CLK
4 ENABLE
Name Description
T1LD 16-bit load value register
T1VAL 16-bit timer value register
T1CON Control register
T1CLRI Clear interrupt register
T1CAP Capture register
T1STA Status register
Description
Load value. The up/down counter is periodically loaded with this value if
periodic mode is selected (T1CON[3]=1). LOAD writes during up/down
counter timeout events are delayed until the event has passed.
Description
Current count. Reflects the current up/down counter value. Value delayed
two PCLK cycles due to clock synchronizers.
Description
Reserved.
Event select. Used to enable and disabling the capture of events. Used in
conjunction with the EVENT select range: when a selected event occurs
the current value of the up/down counter is captured in T1CAP.
0: Events are not captured
1: Events are captured
Event select range. Timer event select range (0 to 15).
Reload control. RLD is only used for periodic mode; this bit allows the user
to select whether the up/down counter should be reset only on a timeout
event or also when T1CLRI[0] is set.
1: resets the up/down counter when T1CLRI[0] is set
0: up/down counter is only reset on a timeout event
Clock select. Used to select a timer clock from the four available clock sources.
00: PCLK.
01: HCLK.
10: LFOSC. 32 KHz OSC
11: HFXTAL. 16 MHz OSC or XTAL, Dependent on the value in CLKCON0[11].
Timer enable. Used to enable and disable the timer. Clearing this bit resets
the timer, including the T1VAL register.
0: DIS. Timer is disabled (default).
1: EN. Timer is enabled.
ADuCM320 Hardware Reference Manual
Rev. C | Page 160 of 196
Reset RW
0x0000 RW
0x0000 R
0x000A RW
0x0000 W
0x0000 R
0x0000 R
Reset Access
0x0 RW
Reset Access
0x0 R
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW