Analog Devices ADuCM320 Hardware Reference Manual page 136

UG-498
Bits Bit Name
5 LSB
4 WOM
3 CPOL
2 CPHA
1 MASEN
0 ENABLE
SPI DMA Enable Register
Address: 0x40030014, Reset: 0x0000, Name: SPI1DMA
Table 192. Bit Descriptions for SPI1DMA
Bits Bit Name
[15:3] RESERVED
2 IENRXDMA
1 IENTXDMA
0 ENABLE
Transfer Byte Count Register
Address: 0x40030018, Reset: 0x0000, Name: SPI1CNT
Table 193. Bit Descriptions for SPI1CNT
Bits Bit Name
[15:8] RESERVED
[7:0] COUNT
Description
LSB first transfer enable.
0: MSB transmitted first
1: LSB transmitted first
SPI wired Or mode.
0: normal output levels
1: enables open circuit data output enable. External pull-ups required on
data out pins
Serial clock polarity.
0: serial clock idles low
1: serial clock idles high
Serial clock phase mode.
0: serial clock pulses at the end of each serial bit transfer
1: serial clock pulses at the beginning of each serial bit transfer
Master mode enable.
0: enable slave mode
1: enable master mode
SPI enable.
0: disable the SPI
1: enable the SPI
Description
Reserved.
Enable receive DMA request.
0: disable RX DMA interrupt
1: enable RX DMA interrupt
Enable transmit DMA request.
0: disable TX DMA interrupt
1: enable TX DMA interrupt
Enable DMA for data transfer. Set by user code to start a DMA transfer.
Cleared by user code at the end of DMA transfer. This bit needs to be
cleared to prevent extra DMA request to the µDMA controller.
Description
Reserved.
Transfer byte count. COUNT indicates the number of bytes to be
transferred. Count is used in both receive and transmit transfer types. The
COUNT value assures that a master mode transfer terminates at the proper
time and that 16-bit DMA transfers are byte padded or discarded as
required to match odd transfer counts. Reset by clearing SPI1CON[0] or if
SPI1CNT is updated.
Rev. C | Page 136 of 196
ADuCM320 Hardware Reference Manual
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RW