Analog Devices ADuCM320 Hardware Reference Manual page 55

ADuCM320 Hardware Reference Manual
Bits Bit Name
3 IRQ4EN
[2:0] IRQ4MDE
External Interrupt Configuration Register 2
Address: 0x40002428, Reset: 0x0000, Name: EI2CFG
Table 59. Bit Descriptions for EI2CFG
Bits Bit Name
15:4 RESERVED
3 IRQ8EN
[2:0] IRQ8MDE
External Interrupt Clear Register
Address: 0x40002430, Reset: 0x0000, Name: EICLR
Table 60. Bit Descriptions for EICLR
Bits Bit Name
[15:9] RESERVED
8 IRQ8
7 IRQ7
6 RESERVED
5 IRQ5
4 IRQ4
3 RESERVED
2 IRQ2
1 IRQ1
0 IRQ0
Description
External Interrupt 4 enable bit.
0: External Interrupt 4 disabled
1: External Interrupt 4 enabled
External Interrupt 4 mode registers.
000: rising edge
001: falling edge
010: rising or falling edge
011: high level
100: low level
101: falling edge (same as 001)
110: rising or falling edge (same as 010)
111: high level (same as 011)
Description
Reserved.
External Interrupt 8 enable bit.
0: External Interrupt 8 disabled
1: External Interrupt 8 enabled
External Interrupt 8 mode registers.
000: rising edge
001: falling edge
010: rising or falling edge
011: high level
100: low level
101: falling edge (same as 001)
110: rising or falling edge (same as 010)
111: high level (same as 011)
Description
Reserved.
External interrupt 8. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
External interrupt 7. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
Reserved.
External interrupt 5. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
External interrupt 4. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
External interrupt 2. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
External interrupt 1. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
External interrupt 0. Set to 1 to clear an internal interrupt flag. Cleared
automatically by hardware.
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UG-498
Reset Access
0x0 RW
0x0 RW
Reset Access
0x0
0x0 RW
0x0 RW
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW