Memory Organization - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
Communication
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UART
Industry standard, 16450 UART peripheral
o
Support for DMA
o
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Two I 2 Cs
2-byte transmit and receive FIFOs for the master and slave
o
Support for DMA
o
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Two SPIs
Master or slave mode with separate 4-byte Rx and Tx FIFOs
o
Rx and Tx DMA channels
o
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16-bit PWM with seven output channels
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Multiple GPIO pins
Processing
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ARM Cortex-M3 processor, operating from an internal 80 MHz system clock
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Two 128 kB Flash/EE memory, 32 kB SRAM
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In-circuit download and debug via serial wire
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On-chip MDIO download capability
On-Chip Peripherals
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Three general-purpose timers
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Wake-up timer
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Watchdog timer
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32-element programmable logic array (PLA)
Packages and Temperature Range
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6 mm × 6 mm, 96-ball BGA package, −40°C to +85°C
Tools
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Low cost development system
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Third-party compiler and emulator tool support
Applications
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Optical networking—10 G, 40 G, and 100 G modules
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Industrial control and automation systems
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Smart sensors, precision instrumentation
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Base station systems

MEMORY ORGANIZATION

The ADuCM320 memory organization is described in this section.
Features
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Cortex-M3 memory system features
Predefined memory map.
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Support for bit-band operation for atomic operations.
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Unaligned data access.
o
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ADuCM320 on-chip peripherals are accessed via memory mapped registers, situated in the bit-band region.
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User memory sizes options:
32 kB SRAM
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Two 128 kB Flash/EE memory
o
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On-chip kernel for manufacturer data and in-circuit download
ADuCM320 Hardware Reference Manual
Rev. C | Page 8 of 196