Analog Devices ADuCM320 Hardware Reference Manual page 115

ADuCM320 Hardware Reference Manual
Bits Bit Name
3 RESERVED
2 LOOPBACK
1 COMPETE
0 MASEN
Master Status Register
Address: 0x40003404, Reset: 0x6000, Name: I2C1MSTA
Table 158. Bit Descriptions for I2C1MSTA
Bits Bit Name
15 RESERVED
14 SCL_FILTERED
13 SDA_FILTERED
12 MTXUFLOW
11 MSTOP
10 LINEBUSY
9 MRXOF
8 TCOMP
7 NACKDATA
6 MBUSY
5 ALOST
Description
Reserved. A value of 0 should be written to this bit.
Internal loopback enable. Note that is also possible for the master to loop
back a transfer to the slave as long as the device address corresponds, i.e.
external loopback.
0: SCL and SDA out of the device are not muxed onto their corresponding
inputs.
1: SCL and SDA out of the device are muxed onto their corresponding
inputs.
Start back-off disable. Setting this bit enables the device to compete for
ownership even if another device is currently driving a START condition.
Master enable. The master should be disabled when not in use as this gates
the clock to the master and saves power. This bit should not be cleared until a
transaction has completed; see the TCOMP bit in the master status register.
0: master is disabled
1: master is enabled
Description
Reserved.
State of SCL line. This bit is the output of the glitch-filter on SCL. SCL is
always pulled high when undriven.
State of SDA line. This bit is the output of the glitch-filter on SDA. SDA is
always pulled high when undriven.
Master transmit underflow. Asserts when the I
transaction due to Tx-FIFO empty condition. This bit is asserted only when
the IENMTX bit is set.
STOP driven by this I 2 C Master. Asserts when this I2C master drives a STOP
condition on the I 2 C bus. This bit, when asserted, can indicate a transaction
completion, Tx-underflow, Rx-overflow or a NACK by the slave. This is different
from the TCOMP as this bit is not asserted when the STOP condition occurs
due to any other I 2 C master. No interrupt is generated for the assertion of
this bit. However, if IENCMP is 1, every STOP condition generates an
interrupt and this bit can be read. When this bit is read, it clears status.
Line is busy. Asserts when a START is detected on the I
when a STOP is detected on the I
Master Receive FIFO overflow. Asserts when a byte is written to the receive
FIFO when the FIFO is already full. When the bit is read it clears status.
Transaction complete or stop detected. Transaction complete. This bit
asserts when a STOP condition is detected on the I
interrupt is generated when this bit asserts. This bit only asserts if the
master is enabled (MASEN = 1). This bit should be used to determine when
it is safe to disable the master. It can also be used to wait for another master
transaction to complete on the I
When this bit is read, it clears status. This bit can drive an interrupt.
ACK not received in response to data write. This bit asserts when an ACK is
not received in response to a data write transfer. If IENACK is 1, an interrupt
is generated when this bit asserts. This bit can drive an interrupt. This bit is
cleared on a read of the I2C1MSTA register.
Master busy. This bit indicates that the master state machine is servicing a
transaction. It is clear if the state machine is idle or another device has
control of the I 2 C bus.
Arbitration lost. This bit asserts if the master loses arbitration. If IENALOST
is 1, an interrupt is generated when this bit asserts. This bit is cleared on a
read of the I2C1MSTA register. This bit can drive an interrupt.
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2 C master ends the
2 C bus. Deasserts
2 C bus.
2 C bus. If IENCMP is 1, an
2 C bus when this master loses arbitration.
UG-498
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x1 R
0x1 R
0x0 RC
0x0 RC
0x0 R
0x0 RC
0x0 RC
0x0 RC
0x0 R
0x0 RC