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UG-498
ECC Enable/Disable, Error Response Register
Address: 0x40018064, Reset: 0x00000000, Name: FEEECCCONFIG
This register is key-protected, so the key (0x5ECCACCE) must be entered in FEEKEY. After writing to FEECCCONFIG the key is cleared.
Table 112. Bit Descriptions for FEEECCCONFIG
Bits
Bit Name
[31:5]
RESERVED
[4:3]
ECCCMDINTEN
[2:1]
ECCCMDAHBEN
0
ECCDISABLE
Flash 0 ECC Error Address Register
Address: 0x40018074, Reset: 0x00000000, Name: FEEECCADDR0
Table 113. Bit Descriptions for FEEECCADDR0
Bits
Bit Name
[31:19]
RESERVED
[18:0]
VALUE
Flash 1 ECC Error Address Register
Address: 0x40018078, Reset: 0x00000000, Name: FEEECCADDR1
Table 114. Bit Descriptions for FEEECCADDR1
Bits
Bit Name
[31:19]
RESERVED
[18:0]
VALUE
Description
Reserved.
Interrupt enabled (Flash Interrupt) when an ECC error happens during a read.
Bits
Description
00
Interrupt is not generated if an ECC error occurs while reading from flash.
01
Interrupt enable d only if a 2-bit error is detected during a read from Flash 0 or
Flash 1.
10
Interrupt enable d only if a 1-bit error is detected during a read from Flash 0 or
Flash 1.
11
Interrupt enable d if either a 2-bit error or 1-bit error is detected during a read
from Flash 0 or Flash 1.
Generates a system exception (Bus Fault) when an ECC error happens during a read.
Bits
Description
00
Exception is not generated if an ECC error occurs while reading from flash.
01
Exception enable d only if a 2-bit error is detected during a read from Flash 0 or
Flash 1.
10
Exception enable d only if a 1-bit error is detected during a read from Flash 0 or
Flash 1.
11
Exception enable d if either a 2-bit error or 1-bit error is detected during a read
from Flash 0 or Flash 1.
Setting this bit to 1 disables ECC. When ECC is disabled, ECC module is bypassed. When
a read to a flash location is carried out, corresponding to the requested address, LSB 32-
bit or MSB 32-bit raw data is returned to the bus.
Description
Reserved.
This register has the address of flash0 for which ECC error is detected.
Description
Reserved.
This register has the address of flash0 for which ECC error is detected.
ADuCM320 Hardware Reference Manual
Rev. C | Page 88 of 196
Reset
Access
0x0
R
0x0
RW
0x0
RW
0x0
RW
Reset
Access
0x0
R
0x0
R
Reset
Access
0x0
R
0x0
R
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