Analog Devices ADuCM320 Hardware Reference Manual page 68

UG-498
DMA Configuration Register
Address: 0x40010004, Reset: 0x00000000, Name: DMACFG
Table 79. Bit Descriptions for DMACFG
Bits Bit Name
[31:1] RESERVED
0 MENABLE
DMA Channel Primary Control Data Base Pointer Register
Address: 0x40010008, Reset: 0x00000000, Name: DMAPDBPTR
The DMAPDBPTR register must be programmed to point to the primary channel control base pointer in the system memory. The
amount of system memory that must be assigned to the DMA controller depends on the number of DMA channels used and whether the
alternate channel control data structure is used. This register cannot be read when the DMA controller is in the reset state.
Table 80. Bit Descriptions for DMAPDBPTR
Bits Bit Name
[31:0] CTRLBASEPTR
DMA Channel Alternate Control Data Base Pointer Register
Address: 0x4001000C, Reset: 0x00000100, Name: DMAADBPTR
The DMAADBPTR read-only register returns the base address of the alternate channel control data structure. This register removes the
necessity for application software to calculate the base address of the alternate data structure. This register cannot be read when the DMA
controller is in the reset state.
Table 81. Bit Descriptions for DMAADBPTR
Bits Bit Name
[31:0] ALTCBPTR
DMA Channel Software Request Register
Address: 0x40010014, Reset: 0x00000000, Name: DMASWREQ
The DMASWREQ register enables the generation of software DMA request. Each bit of the register represents the corresponding channel
number in the DMA controller. M is the number of DMA channels
Table 82. Bit Descriptions for DMASWREQ
Bits Bit Name
[31:14] RESERVED
[13:0] CHSWREQ
Description
Reserved. Undefined.
Controller enable.
0: disable controller
1: enable controller
Description
Pointer to the base address of the primary data structure. 5 + log(2) M LSBs
are reserved and must be written 0. M is the number of channels.
Description
Base address of the alternate data structure.
Description
Reserved.
Generate software request. Set the appropriate bit to generate a software DMA
request on the corresponding DMA channel.
Bit 0 corresponds to DMA Channel 0, and Bit M-1 corresponds to DMA Channel M-1.
When written:
Bit [C] = 0, does not create a DMA request for Channel C.
Bit [C] = 1, generates a DMA request for Channel C.
These bits are automatically cleared by the hardware after the corresponding
software request completes.
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ADuCM320 Hardware Reference Manual
Reset Access
0x0 W
0x0 W
Reset Access
0x0 RW
Reset Access
0x100 R
Reset Access
0x0 W
0x0 W