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ADuCM320 Hardware Reference Manual
CLOCK
CYCLE
NUMBER
SPI CLOCK
(CPOL = 0)
SPI CLOCK
(CPOL = 1)
MOSI
(FROM
XX
MASTER)
MISO
(FROM
XX
SLAVE)
CS
CLOCK
CYCLE
NUMBER
SPI CLOCK
(CPOL = 0)
SPI CLOCK
(CPOL = 1)
MOSI
XX
(FROM
MASTER)
MISO
(FROM
XX
SLAVE)
CS
t
1
SPI Data Underrun and Overflow
If the transmit zeros enable bit, ZEN (SPIxCON[7]), is cleared, the last byte from the previous transmission is shifted out when a transfer
is initiated with no valid data in the FIFO. If ZEN is set to 1, 0s are transmitted when a transfer is initiated with no valid data in the FIFO.
If the Rx overflow overwrite enable bit, RXOF (SPIxCON[8]), is set, the valid data in the Rx FIFO is overwritten by the new serial byte
received if there is no space left in the FIFO. If RXOF is cleared, the new serial byte received is discarded if there is no space left in the FIFO.
When the RXOF is set, the contents of the SPI Rx FIFO are undefined and its contents should be discarded by user code.
Full Duplex Operation
Simultaneous reads/writes are supported on the SPI.
When implementing full duplex transfers in master mode, use the following procedure:
1.
Initiate a transfer sequence via a transmit on the MOSI pin. Set SPIxCON[6] = 1. If interrupts are enabled, interrupts are triggered
when a transmit interrupt occurs but not when a byte is received.
2.
If you are using interrupts, the SPI Tx interrupt indicated by SPIxSTA[5] or the Tx FIFO underrun interrupt (SPIxSTA[4]) is asserted
approximately 3 × SPICLK to 4 × SPICLK periods into the transfer of the first byte. Reload a byte into the Tx FIFO, if necessary, by
writing to SPIxTX.
The first byte received via the MISO pin does not update the Rx FIFO status bits (SPIxSTA[10:8]) until 12 × SPICLK periods after CS
3.
has gone low. Therefore, two transmit interrupts may occur before the first receive byte is ready to be handled.
4.
After the last transmit interrupt has occurred, it may be necessary to read two more bytes. It is recommended that SPIxSTA[10:8] are
polled outside of the SPI interrupt handler after the last transmit interrupt is handled.
1
2
3
MSB
6
5
MSB
6
5
t
1
Figure 22. SPI Transfer Protocol CPHA = 0
1
2
3
MSB
6
5
MSB
6
5
Figure 23. SPI Transfer Protocol CPHA = 1
4
5
6
4
3
2
4
3
2
4
5
6
4
3
2
4
3
2
Rev. C | Page 125 of 196
7
8
1
LSB
XX
1
LSB
XX
t
t
2
3
7
8
1
LSB
XX
1
LSB
XX
t
t
2
3
UG-498
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