Digital Port Multiplex; Changes To Table 121 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

DIGITAL PORT MULTIPLEX

This block provides control over the GPIO functionality of specified pins because some of the pins offer the choice to work as a GPIO or
to have other specific functions.
Table 121. GPIO Multiplex Table
GPIO
GP0—GP0CON Controls These Bits
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7 1
GP1—GP1CON Controls These Bits
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GP2—GP2CON Controls These Bits
P2.0
P2.1 2
P2.2
P2.3
P2.4
00 01
GPIO SPI0 SCLK
(GP0CON[1:0] = 0x0) (GP0CON[1:0] = 0x1)
GPIO SPI0 MISO
(GP0CON[3:2] = 0x0) (GP0CON[3:2] = 0x1)
GPIO SPI0 MOSI
(GP0CON[5:4] = 0x0) (GP0CON[5:4] = 0x1)
GPIO/IRQ0 SPI0 CS
(GP0CON[7:6] = 0x0) (GP0CON[7:6] = 0x1)
GPIO I2C0 SCL
(GP0CON[9:8] = 0x0) (GP0CON[9:8] = 0x1)
GPIO I2C0 SDA
(GP0CON[11:10] = 0x0) (GP0CON[11:10] = 0x1)
GPIO I2C1 SCL
(GP0CON[13:12] = 0x0) (GP0CON[13:12] = 0x1)
GPIO I2C1 SDA
(GP0CON[15:14] = 0x0) (GP0CON[15:14] = 0x1)
GPIO UART SIN
(GP1CON[1:0] = 0x0) (GP1CON[1:0] = 0x1)
GPI0 UART SOUT
(GP1CON[3:2] = 0x0) (GP1CON[3:2] = 0x1)
GPIO PWM0
(GP1CON[5:4] = 0x0) (GP1CON[5:4] = 0x1)
GPIO PWM1
(GP1CON[7:6] = 0x0) (GP1CON[7:6] = 0x1)
GPIO PWM2
(GP1CON[9:8] = 0x0) (GP1CON[9:8] = 0x1)
GPIO PWM3
(GP1CON[11:10] = 0x0) (GP1CON[11:10] = 0x1)
GPIO PWM4
(GP1CON[13:12] = 0x0) (GP1CON[13:12] = 0x1)
GPIO/IRQ1 PWM5
(GP1CON[15:14] = 0x0) (GP1CON[15:14] = 0x1)
GPIO/IRQ2 PWMTRIP
(GP2CON[1:0] = 0x0) (GP2CON[1:0] = 0x1)
GPIO/IRQ4 PORB
(GP2CON[5:4] = 0x0) (GP2CON[5:4] = 0x1)
GPIO/BM
(GP2CON[7:6] = 0x0)
GPIO/IRQ5 ADCCONV
(GP2CON[9:8] = 0x0) (GP2CON[9:8] = 0x1)
Rev. C | Page 94 of 196
ADuCM320 Hardware Reference Manual
Configuration Modes
10
PLACLK0
(GP0CON[7:6] = 0x2)
ECLKIN
(GP1CON[1:0] = 0x2)
PLACLK1
(GP1CON[3:2] = 0x2)
SPI1 SCLK
(GP1CON[9:8] = 0x2)
SPI1 MISO
(GP1CON[11:10] = 0x2)
SPI1 MOSI
(GP1CON[13:12] = 0x2)
SPI1 CS
(GP1CON[15:14] = 0x2)
PLACLK2
(GP2CON[1:0] = 0x2)
CLKOUT
(GP2CON[5:4] = 0x2)
PWM6
(GP2CON[9:8] = 0x2)
11
PLAI[0]
(GP0CON[1:0] = 0x3)
PLAI[1]
(GP0CON[3:2] = 0x3)
PLAI[2]
(GP0CON[5:4] = 0x3)
PLAI[3]
(GP0CON[7:6] = 0x3)
PLAO[2]
(GP0CON[9:8] = 0x3)
PLAO[3]
(GP0CON[11:10] = 0x1)
PLAO[4]
(GP0CON[13:12] = 0x3)
PLAO[5]
(GP0CON[15:14] = 0x3)
PLAI[4]
(GP1CON[1:0] = 0x3)
PLAI[5]
(GP1CON[3:2] = 0x3)
PLAI[6]
(GP1CON[5:4] = 0x3)
PLAI[7]
(GP1CON[7:6] = 0x3)
PLAO[10]
(GP1CON[9:8] = 0x3)
PLAO[11]
(GP1CON[11:10] = 0x3)
PLAO[12]
(GP1CON[13:12] = 0x3)
PLAO[13]
(GP1CON[15:14] = 0x3)
PLAI[8]
(GP2CON[1:0] = 0x3)
PLAI[10]
(GP2CON[5:4] = 0x3)
PLAO[18]
GP2CON[9:8] = 0x3)