Register Summary: Idac; Register Details: Idac - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: IDAC

The CPU accesses the IDAC circuit over a die to die interface (D2D) which increases the execution times of ldr and str instructions. The
32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute.
Table 27. IDAC Register Summary
Address Name
0x40086800 IDAC0DAT
0x40086804 IDAC0CON
0x40086808 IDAC1DAT
0x4008680C IDAC1CON
0x40086810 IDAC2DAT
0x40086814 IDAC2CON
0x40086818 IDAC3DAT
0x4008681C IDAC3CON

REGISTER DETAILS: IDAC

IDAC0 Data Register
Address: 0x40086800, Reset: 0x00000000, Name: IDAC0DAT
Table 28. Bit Descriptions for IDAC0DAT
Bits Bit Name Description
[31:28] RESERVED Reserved. Write 0.
[27:17] DATH IDAC0 high data.
[16:12] DATL IDAC0 low data.
[11:4] RESERVED Reserved.
3 SYNC3 IDAC3 sync bit. Setting the SYNC3 bits of all IDAC channels to 1 prevents IDAC3 from updating.
When the SYNC3 bit of any of the IDAC channels is 0, IDAC3 updates immediately when it is written.
2 SYNC2 IDAC2 sync bit. Setting the SYNC2 bits of all IDAC channels to 1 prevents IDAC2 from updating.
When the SYNC2 bit of any of the IDAC channels is 0, IDAC2 updates immediately when it is written.
1 SYNC1 IDAC1 sync bit. Setting the SYNC1 bits of all IDAC channels to 1 prevents IDAC1 from updating.
When the SYNC1 bit of any of the IDAC channels is 0, IDAC1 updates immediately when it is written.
0 SYNC0 IDAC0 sync bit. Setting the SYNC0 bits of all IDAC channels to 1 prevents IDAC0 from updating.
When the SYNC0 bit of any of the IDAC channels is 0, IDAC0 updates immediately when it is written.
IDAC0 Control Register
Address: 0x40086804, Reset: 0x01, Name: IDAC0CON
Table 29. Bit Descriptions for IDAC0CON
Bits Bit Name Description
7 CLRB IDAC0 clear bit.
0: clear IDAC0DAT
1: enable write
6 SHT_EN IDAC0 shutdown enable. Enables automatic shutdown in case of overtemperature.
0: disable this function
1: enable this function
[5:2] BW IDAC0 bandwidth. See the IDAC Output Filter section for more details.
1 PUL IDAC0 pull-down.
0: disable the pull-down current source
1: enable the pull-down current source
0 PD IDAC0 power down.
0: powers up IDAC0
1: powers down IDAC0
Description
IDAC0 data register
IDAC0 control register
IDAC1 data register
IDAC1 control register
IDAC2 data register
IDAC2 control register
IDAC3 data register
IDAC3 control register
Rev. C | Page 40 of 196
ADuCM320 Hardware Reference Manual
Reset RW
0x00000000 RW
0x01 RW
0x00000000 RW
0x01 RW
0x00000000 RW
0x01 RW
0x00000000 RW
0x01 RW
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x1 RW