Register Summary: I2C1; Register Details: I2C1 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: I2C1

Table 156. I2C1 Register Summary
Address Name
0x40003400 I2C1MCON
0x40003404 I2C1MSTA
0x40003408 I2C1MRX
0x4000340C I2C1MTX
0x40003410 I2C1MRXCNT
0x40003414 I2C1MCRXCNT
0x40003418 I2C1ADR0
0x4000341C I2C1ADR1
0x40003424 I2C1DIV
0x40003428 I2C1SCON
0x4000342C I2C1SSTA
0x40003430 I2C1SRX
0x40003434 I2C1STX
0x40003438 I2C1ALT
0x4000343C I2C1ID0
0x40003440 I2C1ID1
0x40003444 I2C1ID2
0x40003448 I2C1ID3
0x4000344C I2C1FSTA
0x40003450 I2C1SHCON

REGISTER DETAILS: I2C1

Master Control Register
Address: 0x40003400, Reset: 0x0000, Name: I2C1MCON
Table 157. Bit Descriptions for I2C1MCON
Bits Bit Name
[15:12] RESERVED
11 MTXDMA
10 MRXDMA
9 RESERVED
8 IENCMP
7 IENACK
6 IENALOST
5 IENMTX
4 IENMRX
Description
Master control register
Master status register
Master receive data register
Master transmit data register
Master receive data count register
Master current receive data count register
1st master address byte register
2nd master address byte register
Serial clock period divisor register
Slave control register
Slave I 2 C status/error/IRQ register
Slave receive register
Slave transmit register
Hardware general call ID register
1st slave address device ID register
2nd slave address device ID register
3rd slave address device ID register
4th slave address device ID register
Master and slave FIFO status register
Master and slave shared control register
Description
Reserved.
Enable master Tx DMA request.
0: disable DMA mode
1: enable I 2 C master DMA Tx requests
Enable master Rx DMA request.
0: disable DMA mode
1: enable I C master DMA Rx requests
2
Reserved.
Transaction completed (or stop detected) interrupt enable.
0: an interrupt is not generated when a STOP is detected.
1: an interrupt is generated when a STOP is detected.
ACK not received interrupt enable.
0: ACK not received interrupt disable
1: ACK not received interrupt enable
Arbitration lost interrupt enable.
0: arbitration lost interrupt disable
1: arbitration lost interrupt enable
Transmit request interrupt enable.
0: transmit request interrupt disable
1: transmit request interrupt enable
Receive request interrupt enable.
0: receive request interrupt disable
1: receive request interrupt enable
Rev. C | Page 114 of 196
ADuCM320 Hardware Reference Manual
Reset RW
0x0000 RW
0x6000 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 R
0x0000 RW
0x0000 RW
0x1F1F RW
0x0000 RW
0x0001 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 W
Reset Access
0x0 R
0x0 W
0x0 W
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW