Analog Devices ADuCM320 Hardware Reference Manual page 133

ADuCM320 Hardware Reference Manual
Bits Bit Name
13 CSFLG
12 CSERR
11 RXS
[10:8] RXFSTA
7 RXOF
6 RX
5 TX
4 TXUR
[3:1] TXFSTA
0 IRQ
Description
Detected a falling edge on CS, in CONT mode. This bit causes an interrupt.
This can be used to identify the start of an SPI data frame.
0: cleared to 0 when the status register is read.
1: set to 1 when there was a falling edge in CS line, when the device was in
master mode, continuous transfer, high frequency mode and CSIRQ_EN
was asserted.
Detected a CS error condition.
0: cleared to 0 when the status register is read.
1: set to 1 when the CS line was de-asserted abruptly, even before the full
byte of data was transmitted completely. This bit causes an interrupt.
SPI Rx FIFO excess bytes present.
0: cleared to 0 when the number of bytes in the FIFO is equal or less than
the number in SPI1CON[15:14].
1: set to 1 when there are more bytes in the Rx FIFO than indicated in the
MOD bits in SPI1CON.
SPI Rx FIFO status.
000: Rx FIFO empty
001: 1 valid byte in FIFO
010: 2 valid bytes in the FIFO
011: 3 valid bytes in the FIFO
100: 4 valid bytes in the FIFO
SPI Rx FIFO overflow.
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when the Rx FIFO was already full when new data was loaded to the
FIFO. This bit generates an interrupt except when RFLUSH is set in SPI1CON.
SPI Rx IRQ. Not available in DMA mode. Set when a receive interrupt occurs.
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when TIM in SPI1CON is cleared and the required number of
bytes have been received.
SPI Tx IRQ. Status bit. Not available in DMA mode.
0: CLR. Cleared to 0 when the SPI1STA register is read.
1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in
SPI1CON is set and the required number of bytes have been transmitted.
SPI Tx FIFO underflow.
0: cleared to 0 when the SPI1STA register is read.
1: set to 1 when a transmit is initiated without any valid data in the Tx FIFO.
This bit generates an interrupt except when TFLUSH is set in SPI1CON.
SPI Tx FIFO status.
000: Tx FIFO empty
001: 1 valid byte in FIFO
010: 2 valid bytes in FIFO
011: 3 valid bytes in FIFO
100: 4 valid bytes in FIFO
SPI interrupt status.
0: cleared to 0 after reading SPI1STA.
1: set to 1 when an SPI based interrupt occurs.
Rev. C | Page 133 of 196
UG-498
Reset Access
0x0 RC
0x0 RC
0x0 R
0x0 R
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 R
0x0 RC