Revision History - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
Wake-Up Timer ............................................................................ 169
Wake-Up Timer Features ........................................................ 169
Wake-Up Timer Block Diagram ............................................. 169
Wake-Up Timer Overview ...................................................... 169
Wake-Up Timer Operation ..................................................... 169
Register Summary: Wake-Up Timer ..................................... 172
Register Details: Wake-Up Timer .......................................... 172
PWM .............................................................................................. 176
PWM Features .......................................................................... 176
PWM Overview ........................................................................ 176
PWM Operation ....................................................................... 176
PWM Interrupt Generation .................................................... 179
Register Summary: PWM ....................................................... 180

REVISION HISTORY

1/2017-Rev. B to Rev. C
Changes to Clocking Architecture Operation Section .............. 12
Changes to ADC Circuit Features Section .................................. 21
Changes to ADC Circuit Overview Section ............................... 22
Changes to Single-Ended Mode Section and Differential
Section .............................................................................................. 23
Changes to ADC Voltage Reference Selection Section.............. 26
Changes to Table 23 ........................................................................ 34
Added IDAC Thermal Shutdown Section ................................... 39
Changes to Writing to Flash Section ............................................ 75
Changes to Table 121 ...................................................................... 94
Changes to Table 182 .................................................................... 130
2/2016-Rev. A to Rev. B
Changes to Table 7 .......................................................................... 14
Changes to Table 12 ........................................................................ 28
Changes to Protection, Integrity Section ..................................... 72
Added ECC Error Handling Section, ECC Error During Read
Section, and ECC Error During Execution of Sign Command
Section .............................................................................................. 76
Changes to Table 95 and Table 96 ................................................ 80
Added ECC Enable/Disable, Error Response Register Section,
Flash 0 ECC Error Address Register Section, Flash 1 ECC Error
Address Register Section, and Table 112 to Table 114;
Renumbered Sequentially .............................................................. 86
Added MDIO Interrupt Power-Up Register Write Sequence
Section ............................................................................................ 184
1/2015-Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Register Access Conventions Section ........................ 6
Changes to Introduction to the ADuCM320 Section .................. 7
Moved Register Summary: Clock Architecture Section ............ 12
Changes to Table 4 and Clocking Architecture Operation
Section .............................................................................................. 12
ADuCM320 Hardware Reference Manual
Register Details: PWM ............................................................ 180
MDIO ............................................................................................. 184
MDIO Features ......................................................................... 184
MDIO Overview ....................................................................... 184
MDIO Operation ...................................................................... 184
Block Switching ........................................................................ 186
Register Summary: MDIO Interface (MDIO) ...................... 191
Register Details: MDIO ........................................................... 191
Hardware Design Considerations .............................................. 194
Typical System Configuration ................................................ 194
Serial Wire Debug Interface .................................................... 196
Change to Table 5 ........................................................................... 13
Changes to Table 6 and Table 7 .................................................... 14
Added Clocking Status Register Section and Table 8;
Renumbered Sequentially ............................................................. 15
Changes to Debug Support Section ............................................. 19
Changes to ADC Voltage Reference Selection Section ............. 26
Added Figure 8; Renumbered Sequentially ................................ 27
Change to Table 14 ......................................................................... 30
Changes to Table 16 ....................................................................... 31
Changes to Table 17 ....................................................................... 32
Changes to Table 22 ....................................................................... 33
Changes to Table 25 ....................................................................... 36
Changes to Case 2-Turn On IDAC2 but to Set the Output to
0 mA with the Lowest Possible Offset Section ........................... 38
Changes to Table 74 ....................................................................... 62
Changes to Table 75 ....................................................................... 64
Changes to Table 76 ....................................................................... 65
Added Aborting DMA Transfers Section .................................... 65
Changed Top of Flash Blocks Section to Reserved Flash
Locations Section............................................................................ 73
Changes to Erasing Flash Section and Signature Section ......... 74
Changes to CPU Execution Speed Section ................................. 76
Changes to Memory Cache Section ............................................. 77
Changes to Table 95 and Table 96 ................................................ 79
Changes to Cache Status Register Section .................................. 84
Added Table 112 ............................................................................. 84
Changes to Cache Setup Register Section and Cache Key
Register Section .............................................................................. 85
Added Table 113 and Table 114 .................................................... 85
Deleted Shared MDIO Pins Section ............................................ 85
Changes to Digital I/Os Features Section and Digital I/Os
Overview Section............................................................................ 86
Added Inaccessible Bits Section ................................................... 86
Changes to I/O Pull-Up Enable (GPxPUL) Section .................. 87
Changes to Open-Drain Enable (GPxODE) Section ................. 88
Rev. C | Page 4 of 196