Reset; Reset Features; Reset Operation - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

RESET

RESET FEATURES

There are four kinds of resets:
•
External reset
•
Power-on reset
•
Watchdog timeout
•
Software system reset

RESET OPERATION

The software system reset is provided as part of the Cortex-M3 processor. To generate a software system reset, the NVIC_SystemReset()
function must be called. This effectively writes 0x05FA to the top 16 bits of an AIRCR NVIC register. This function along with other
useful functions are defined in the CMSIS header files that are shipped with the tools from third party vendors. The NVIC_SystemReset()
function is defined in the core_cm3.h file.
Analog peripherals have the option of maintaining their state after a software or watchdog reset. This function is enabled by default. It can
be disabled using the LVRST register. Note that while debugging, the software tools generally only issue a software reset; therefore, an
external reset is needed to return registers to their default values.
The GPIO pins and PLA also have the option of maintaining their state after a software or watchdog reset. By default, this function is
enabled. Writing a value of 0x1 to RSTCFG configures the GPIO pins and PLA to reset after a software or watchdog reset. Before writing
to this register, 0x2009 must be written to RSTKEY followed by 0x0426. After the two keys are written to RSTKEY, RSTCFG must be
immediately written.
The RSTSTA register stores the cause for the reset until it is cleared by writing the RSTSTA register. RSTSTA can be used during a reset
exception service routine to identify the source of the reset.
The watchdog timer is enabled by default after a reset. The default timeout period is approximately 32 seconds.
User code should disable the watchdog timer at the start of user code when debugging or if the watchdog timer is not required.
pADI_WDT->T3CON = 0x00;
Table 65. Device Reset Implications
Reset External Pins
Reset to Default State
SWRST Yes 1 /No
WDRST Yes /No
1
External Reset Pin Yes 1
POR Yes 1
1 P2.2 returns to its default state, that is, POR output. It is low only in the case of a POR event; in all other cases, it remains high.
2 GPIOs, PLA, and analog peripherals have the option of retaining their state during a watchdog or software reset.
3 RAM is not valid in the case of a reset following an MDIO download.
Execute Kernel
2 Yes
Yes
2
Yes
Yes
// Disable watchdog timer
Impact
Reset All MMRs
Except RSTSTA
Yes/No 2
Yes/No
2
Yes
Yes
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Reset All
Peripherals Valid SRAM
Yes/No 2 Yes/No 3
Yes/No Yes/No
2 3
Yes Yes/No 3
Yes No
UG-498
RSTSTA After
Reset Event
RSTSTA[3] = 1
RSTSTA[2] = 1
RSTSTA[1] = 1
RSTSTA[0] = 1