Analog Devices ADuCM320 Hardware Reference Manual page 129

ADuCM320 Hardware Reference Manual
Bits Bit Name
[10:8] RXFSTA
7 RXOF
6 RX
5 TX
4 TXUR
[3:1] TXFSTA
0 IRQ
Receive Register
Address: 0x4002C004, Reset: 0x0000, Name: SPI0RX
Table 180. Bit Descriptions for SPI0RX
Bits Bit Name
[15:8] DMA_DATA_BYTE_2
[7:0] DATA_BYTE_1
Transmit Register
Address: 0x4002C008, Reset: 0x0000, Name: SPI0TX
Table 181. Bit Descriptions for SPI0TX
Bits Bit Name
[15:8] DMA_DATA_BYTE_2
[7:0] DATA_BYTE_1
Description
SPI Rx FIFO status.
000: Rx FIFO empty
001: 1 valid byte in FIFO
010: 2 valid bytes in the FIFO
011: 3 valid bytes in the FIFO
100: 4 valid bytes in the FIFO
SPI Rx FIFO overflow.
0: cleared when the SPISTA register is read.
1: set when the Rx FIFO was already full when new data was loaded to the
FIFO. This bit generates an interrupt except when RFLUSH is set in SPI0CON.
SPI Rx IRQ. Not available in DMA mode.
0: cleared when the SPI0STA register is read.
1: set when a receive interrupt occurs. This bit is set when TIM in SPI0CON
is cleared and the required number of bytes have been received.
SPI Tx IRQ. Status bit. Not available in DMA mode.
0: CLR. Cleared to 0 when the SPI0STA register is read.
1: SET. Set to 1 when a transmit interrupt occurs. This bit is set when TIM in
SPI0CON is set and the required number of bytes have been transmitted.
SPI Tx FIFO underflow.
0: cleared to 0 when the SPI0STA register is read.
1: set to 1 when a transmit is initiated without any valid data in the Tx FIFO.
This bit generates an interrupt except when TFLUSH is set in SPI0CON.
SPI Tx FIFO status.
000: Tx FIFO empty
001: 1 valid byte in FIFO
010: 2 valid bytes in FIFO
011: 3 valid bytes in FIFO
100: 4 valid bytes in FIFO
SPI interrupt status.
0: cleared to 0 after reading SPI0STA.
1: set to 1 when an SPI based interrupt occurs.
Description
8-bit receive buffer. These 8-bits are used only in the DMA mode, where all
FIFO accesses happen as half-word access. They return zeros if DMA is
disabled.
8-bit receive buffer.
Description
8-bit transmit buffer. These 8-bits are used only in the DMA mode, where
all FIFO accesses happen as half-word access. They return zeros if DMA is
disabled.
8-bit transmit buffer.
Rev. C | Page 129 of 196
UG-498
Reset Access
0x0 R
0x0 RC
0x0 RC
0x0 RC
0x0 RC
0x0 R
0x0 RC
Reset Access
0x0 R
0x0 R
Reset Access
0x0 W
0x0 W