Analog Devices ADuCM320 Hardware Reference Manual page 135

ADuCM320 Hardware Reference Manual
SPI Configuration Register
Address: 0x40030010, Reset: 0x0000, Name: SPI1CON
Table 191. Bit Descriptions for SPI1CON
Bits Bit Name
[15:14] MOD
13 TFLUSH
12 RFLUSH
11 CON
10 LOOPBACK
9 OEN
8 RXOF
7 ZEN
6 TIM
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in
a transfer. For DMA Rx transfer, these bits should be 00.
00: Tx interrupt occurs when 1 byte has been transferred. Rx interrupt
occurs when 1 or more bytes have been received into the FIFO.
01: Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt
occurs when 2 or more bytes have been received into the FIFO.
10: Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt
occurs when 3 or more bytes have been received into the FIFO.
11: Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt
occurs when the Rx FIFO is full, or 4 bytes present.
SPI Tx FIFO flush enable.
0: clear this bit to disable Tx FIFO flushing.
1: set this bit to flush the Tx FIFO. This bit does not clear itself and should
be toggled if a single flush is required. If this bit is left high, then either the
last transmitted value or "0x00" is transmitted depending on the ZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
SPI Rx FIFO flush enable.
0: clear this bit to disable Rx FIFO flushing.
1: set this bit to flush the Rx FIFO. This bit does not clear itself and should
be toggled if a single flush is required. If this bit is set all incoming data is
ignored and no interrupts are generated. If set and TIM = 0, a read of the
Rx FIFO initiates a transfer.
Continuous transfer enable.
0: DIS. Cleared by user to disable continuous transfer. Each transfer
consists of a single 8-bit serial transfer. If valid data exists in the SPI1TX
register, a new transfer is initiated after a stall period of 1 serial clock cycle.
1: EN. Set by user to enable continuous transfer. In master mode, the
transfer continues until no valid data is available in the Tx register. CS is
asserted and remains asserted for the duration of each 8-bit serial transfer
until Tx is empty.
Loopback enable.
0: cleared by user to be in normal mode.
1: set by user to connect MISO to MOSI and test software.
Slave MISO output enable.
0: clear this bit to disable the output driver on the MISO pin. The MISO pin
is open-circuit when this bit is clear.
1: set this bit for MISO to operate as normal.
SPIRX overflow overwrite enable.
0: cleared by user, the new serial byte received is discarded.
1: set by user, the valid data in the Rx register is overwritten by the new
serial byte received.
Transmit zeros enable.
0: clear this bit to transmit the last transmitted value when there is no valid
data in the Tx FIFO.
1: set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
0: cleared by user to initiate transfer with a read of the SPIRX register.
Interrupt only occurs when Rx is full.
1: set by user to initiate transfer with a write to the SPITX register. Interrupt
only occurs when Tx is empty.
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UG-498
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW