Register Summary: Reset; Register Details: Reset - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: RESET

Table 66. Reset Register Summary
Address
0x40002408
0x4000240C
0x40002440
0x40082C34

REGISTER DETAILS: RESET

Reset Status Register
Address: 0x40002440, Reset: 0x0000, Name: RSTSTA
Table 67. Bit Descriptions for RSTSTA
Bits Bit Name
[15:4] RESERVED
3 SWRST
2 WDRST
1 EXTRST
0 POR
Reset Configuration Register
Address: 0x40002408, Reset: 0x0000, Name: RSTCFG
Table 68. Bit Descriptions for RSTCFG
Bits Bit Name
0 GPIO_PLA_RETAIN
Key Protection for RSTCFG Register
Address: 0x4000240C, Reset: 0x0000, Name: RSTKEY
Table 69. Bit Descriptions for RSTKEY
Bits Bit Name
[15:0] RSTKEY
LV Die Reset Configuration Register
Address: 0x40082C34, Reset: 0x0000, Name: LVRST
Table 70. Bit Descriptions for LVRST
Bits Bit Name
[15:1] RESERVED
0 RETAIN
Name Description
RSTCFG Reset configuration
RSTKEY Key protection for RSTCFG
RSTSTA Reset status
LVRST LV die reset configuration
Description
Software reset. Software reset. Set automatically to 1 when the Cortex-M3
system reset is generated. Cleared by writing 1 to the bit.
Watchdog timeout. Set automatically to 1 when a watchdog timeout occurs.
Cleared by writing 1 to the bit.
External reset. Set automatically to 1 when an external reset occurs.
Cleared by writing 1 to the bit.
Power-on reset. Set automatically when a power-on reset occurs. Cleared
by writing 1 to the bit.
Description
GPIO/PLA retain their status after WDT and software reset.
1: GPIO/PLA do not retain status after watchdog or software reset.
0: GPIO/PLA retain status after watchdog or software reset.
Description
Reset configuration key register. The RSTCFG register is key-protected. Two
writes to the key are necessary to change the value in the RSTCFG register:
first 0x2009, then 0x0426. The RSTCFG register should then be written. A
write to any other register on the APB bus before writing to RSTCFG returns
the protection to the lock state.
Description
Reserved.
LV retains status after WDT and software reset.
0: LV die retains status after watchdog or software reset.
1: LV die does not retain status after watchdog or software reset.
ADuCM320 Hardware Reference Manual
Rev. C | Page 60 of 196
Reset RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
Reset Access
0x0 R
0x0 RW1C
0x0 RW1C
0x0 RW1C
0x0 RW1C
Reset Access
0x0 RW
Reset Access
0x0 RW
Reset Access
0x0 R
0x0 RW