Analog Devices ADuCM320 Hardware Reference Manual page 165

ADuCM320 Hardware Reference Manual
Status Register
Address: 0x4000081C, Reset: 0x0000, Name: T2STA
Table 241. Bit Descriptions for T2STA
Bits Bit Name
[15:8] RESERVED
7 PDOK
6 BUSY
[5:2] RESERVED
1 CAP
0 TMOUT
Description
Reserved.
T2CLRI synchronization. This bit is set automatically when the user sets
T2CLRI[0] = 1. It is cleared automatically when the clear interrupt request
has crossed clock domains and taken effect in the timer clock domain.
0: CLR. The interrupt is cleared in the timer clock domain.
1: SET. T2CLRI[0] is being updated in the timer clock domain.
Timer Busy. This bit informs the user that a write to T2CON is still crossing
into the timer clock domain. This bit should be checked after writing
T2CON and further writes should be suppressed until this bit is cleared.
0: CLR. Timer ready to receive commands to T2CON.
1: SET. Timer not ready to receive commands to T2CON.
Reserved.
Capture event pending.
0: CLR. No capture event is pending.
1: SET. A capture event is pending.
Timeout event occurred. This bit set automatically when the value of the
counter reaches zero while counting down or reaches full scale when
counting up. This bit is cleared when T2CLRI[0] is set by the user.
0: CLR. No timeout event has occurred.
1: SET. A timeout event has occurred.
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UG-498
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R