Changes To Table 16 - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual
Bits Bit Name Description
[7:5] RESERVED Reserved
[4:0] ADCCP Select ADC channel.
0x0: AIN0.
0x1: AIN1.
0x2: AIN2.
0x3: AIN3.
0x4: AIN4.
0x5: AIN5.
0x6: AIN6.
0x7: AIN7.
0x8: AIN8.
0x9: AIN9.
0xA: AIN10.
0xB: AIN11.
0xC: AIN12.
0xD: AIN13.
0xE: AIN14.
0xF: AIN15.
0x10: reserved.
0x11: reserved.
0x12: IDAC3.
0x13: IDAC1.
0x14: IDAC0.
0x15: IDAC2.
0x16: TEMP_SENSOR.
0x17: VREFP_PADC: Connect ADC_REFP to positive input. Note that this pin should not be
measured relative to AGND. This selection is intended for measuring the differential voltage
between the negative input and ADC_REFP.
0x18: PVDD_IDAC2: use this to measure the PVDD supply voltage for IDAC2.
0x19: IOVDD_2: use this to measure half of the IOVDD supply voltage.
0x1A: AVDD_2: use this to measure half of the AVDD supply voltage.
0x1B: VREFN_PADC: connect ADC_REFN to positive input.
0x1C to 0x1F: reserved.
ADC Sequencer Control Register
Address: 0x40086088, Reset: 0x00000000, Name: ADCSEQ
Table 16. Bit Descriptions for ADCSEQ
Bits Bit Name Description
31 ST Sequence restart, used to force sequence to start at first channel when sequence is working.
1: set to 1 to restart the sequencer. Cleared after writing 1.
30 EN Sequence enable.
1: set to 1 to enable the sequencer
29 RESERVED Reserved.
[28:0] CH Select channels included in sequence operation. For each channel:
0: channel is skipped.
1: channel is included in the sequence.
Each bit corresponds to an ADC channel as defined by ADCCHA[4:0]. For example a value of
0x33 (00110011) includes AIN0, AIN1, AIN4, and AIN5 in the sequence and excludes all other
channels.
Rev. C | Page 31 of 196
UG-498
Reset Access
0x0 R
0x1F RW
Reset Access
0x0 W
0x0 W
0x0 R
0x0 RW