Register Summary: I2C0; Register Details: I2C0 - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

REGISTER SUMMARY: I2C0

Table 135. I2C0 Register Summary
Address Name
0x40003000 I2C0MCON
0x40003004 I2C0MSTA
0x40003008 I2C0MRX
0x4000300C I2C0MTX
0x40003010 I2C0MRXCNT
0x40003014 I2C0MCRXCNT
0x40003018 I2C0ADR0
0x4000301C I2C0ADR1
0x40003024 I2C0DIV
0x40003028 I2C0SCON
0x4000302C I2C0SSTA
0x40003030 I2C0SRX
0x40003034 I2C0STX
0x40003038 I2C0ALT
0x4000303C I2C0ID0
0x40003040 I2C0ID1
0x40003044 I2C0ID2
0x40003048 I2C0ID3
0x4000304C I2C0FSTA
0x40003050 I2C0SHCON

REGISTER DETAILS: I2C0

Master Control Register
Address: 0x40003000, Reset: 0x0000, Name: I2C0MCON
Table 136. Bit Descriptions for I2C0MCON
Bits Bit Name
[15:12] RESERVED
11 MTXDMA
10 MRXDMA
9 RESERVED
8 IENCMP
7 IENACK
6 IENALOST
5 IENMTX
4 IENMRX
Description
Master control register
Master status register
Master receive data register
Master transmit data register
Master receive data count register
Master current receive data count register
1st master address byte register
2nd master address byte register
Serial clock period divisor register
Slave control register
Slave I2C0 status/error/IRQ register
Slave receive register
Slave transmit register
Hardware general call ID register
1st slave address device ID register
2nd slave address device ID register
3rd slave address device ID register
4th slave address device ID register
Master and slave FIFO status register
Master and slave shared control register
Description
Reserved.
Enable master Tx DMA request.
0: disable DMA mode
1: enable I2C0 master DMA Tx requests.
Enable master Rx DMA request.
0: disable DMA mode
1: enable I2C0 master DMA Rx requests.
Reserved.
Transaction completed (or stop detected) interrupt enable.
0: an interrupt is not generated when a STOP is detected.
1: an interrupt is generated when a STOP is detected.
ACK not received interrupt enable.
0: ACK not received interrupt disable
1: ACK not received interrupt enable
Arbitration lost interrupt enable.
0: arbitration lost interrupt disable
1: arbitration lost interrupt enable
Transmit request interrupt enable.
0: transmit request interrupt disable
1: transmit request interrupt enable
Receive request interrupt enable.
0: receive request interrupt disable
1: receive request interrupt enable
Rev. C | Page 105 of 196
UG-498
Reset RW
0x0000 RW
0x6000 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 R
0x0000 RW
0x0000 RW
0x1F1F RW
0x0000 RW
0x0001 R
0x0000 R
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 RW
0x0000 W
Reset Access
0x0 R
0x0 W
0x0 W
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW