Analog Devices ADuCM320 Hardware Reference Manual page 145

ADuCM320 Hardware Reference Manual
Bits Bit Name
3 DDCD
2 TERI
1 DDSR
0 DCTS
Scratch Buffer Register
Address: 0x4000501C, Reset: 0x0000, Name: COMSCR
Table 203. Bit Descriptions for COMSCR
Bits Bit Name
[15:8] RESERVED
[7:0] SCR
Fractional Baud Rate Register
Address: 0x40005024, Reset: 0x0000, Name: COMFBR
Table 204. Bit Descriptions for COMFBR
Bits Bit Name
15 FBEN
[14:13] RESERVED
[12:11] DIVM
[10:0] DIVN
Baud Rate Divider Register
Address: 0x40005028, Reset: 0x0001, Name: COMDIV
Table 205. Bit Descriptions for COMDIV
Bits Bit Name
[15:0] DIV
Description
Delta DCD. If set, this bit self clears after COMMSR is read.
0: DCD has not changed state since COMMSR was last read
1: DCD changed state since COMMSR last read
Trailing edge RI. If set, this bit self clears after COMMSR is read.
0: RI has not changed from 0 to 1 since COMMSR last read
1: RI changed from 0 to 1 since COMMSR last read
Delta DSR. If set, this bit self clears after COMMSR is read.
0: DSR has not changed state since COMMSR was last read
1: DSR changed state since COMMSR last read
Delta CTS. If set, this bit self clears after COMMSR is read.
0: CTS has not changed state since COMMSR was last read
1: CTS changed state since COMMSR last read
Description
Reserved.
Scratch. The scratch register is an 8-bit register used to store intermediate
results. The value contained in the scratch register does not affect UART
functionality or performance. Only 8 bits of this register are implemented.
Bit 15 to Bit 8 are read only and always return 0x00 when read. Writable
with any value from 0 to 255. A read returns the last value written.
Description
Fractional baud rate generator enable. The generating of fractional baud
rate can be described by the following formula, and the final baud rate of
UART operation is calculated as Baud rate = ((UCLK/CDPCLK)/(2 × (M +
N/2048)) 16 × COMDIV.
Reserved.
Fractional baud rate M divide bits 1 to 3. This bit should not be 0.
Fractional baud rate N divide bits 0 to 2047.
Description
Baud rate divider. The COMDIV register should not be 0, which is not
specified. The range of allowed DIV values is from 1 to 65535.
Rev. C | Page 145 of 196
UG-498
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
Reset Access
0x0 R
0x0 RW
Reset Access
0x0 RW
0x0 R
0x0 RW
0x0 RW
Reset Access
0x1 RW