Register Summary: General-Purpose Timer 0; Register Details: General-Purpose Timer 0 - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

REGISTER SUMMARY: GENERAL-PURPOSE TIMER 0

Table 221. Timer 0 Register Summary
Address
0x40000000
0x40000004
0x40000008
0x4000000C
0x40000010
0x4000001C

REGISTER DETAILS: GENERAL-PURPOSE TIMER 0

16-Bit Load Value Register
Address: 0x40000000, Reset: 0x0000, Name: T0LD
Table 222. Bit Descriptions for T0LD
Bits Bit Name
[15:0] LOAD
16-Bit Timer Value Register
Address: 0x40000004, Reset: 0x0000, Name: T0VAL
Table 223. Bit Descriptions for T0VAL
Bits Bit Name
[15:0] VAL
Control Register
Address: 0x40000008, Reset: 0x000A, Name: T0CON
Table 224. Bit Descriptions for T0CON
Bits Bit Name
[15:13] RESERVED
12 EVENTEN
[11:8] EVENT
7 RLD
[6:5] CLK
4 ENABLE
Name Description
T0LD 16-bit load value register
T0VAL 16-bit timer value register
T0CON Control register
T0CLRI Clear interrupt register
T0CAP Capture register
T0STA Status register
Description
Load value. The up/down counter is periodically loaded with this value if
periodic mode is selected (T0CON[3]=1). LOAD writes during up/down
counter timeout events are delayed until the event has passed.
Description
Current count. Reflects the current up/down counter value. Value delayed
two PCLK cycles due to clock synchronizers.
Description
Reserved.
Event select. Used to enable and disabling the capture of events. Used in
conjunction with the EVENT select range: when a selected event occurs
the current value of the up/down counter is captured in T0CAP.
0: Events will not be captured.
1: Events will be captured.
Event select range. Timer event select range (0 to 15).
Reload control. RLD is only used for periodic mode; this bit allows the user
to select whether the Up/Down counter should be reset only on a timeout
event or also when T0CLRI[0] is set.
1: resets the up/down counter when T0CLRI[0] is set
0: up/down counter is only reset on a timeout event
Clock select. Used to select a timer clock from the four available clock sources.
00: PCLK.
01: HCLK.
10: LFOSC. 32 KHz OSC.
11: HFXTAL. 16 MHz OSC or XTAL, dependent on the value in CLKCON0[11].
Timer enable. Used to enable and disable the timer. Clearing this bit resets
the timer, including the T0VAL register.
0: DIS. Timer is disabled (default).
1: EN. Timer is enabled.
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UG-498
Reset RW
0x0000 RW
0x0000 R
0x000A RW
0x0000 W
0x0000 R
0x0000 R
Reset Access
0x0 RW
Reset Access
0x0 R
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW