Register Summary: Additional Registers; Register Details: Additional Registers; Changes To Table 22 - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

REGISTER SUMMARY: ADDITIONAL REGISTERS

The CPU accesses these additional registers over a die to die interface (D2D) which increases the execution times of ldr and str instructions.
The 32 bit MMRs have addresses of 0x40087xxx and take 8 CPU cycles at 80 MHz to execute. The 8 bit MMRs have addresses of 0x40081xxx
and take 5 CPU cycles at 80 MHz to execute.
Table 20. Register Summary
Address Name
0x40081400 IBUFCON
0x40087830 AFETEMPC
0x40087834 AFEREFC

REGISTER DETAILS: ADDITIONAL REGISTERS

InBuf Control Bit Register
Address: 0x40081400, Reset: 0x000F, Name: IBUFCON
Table 21. Bit Descriptions for IBUFCON
Bits Bit Name
[15:4] RESERVED
[3:2] IBUF_PD
[1:0] IBUF_BYP
Temperature Sensor Configuration Register
Address: 0x40087830, Reset: 0x00, Name: AFETEMPC
Table 22. Bit Descriptions for AFETEMPC
Bits Bit Name
[7:2] RESERVED
1 CHOP
0 PD
Description
InBuf control bit
Temperature sensor configuration register
Reference configuration register
Description
Reserved.
Power down P/N InBuf separately.
00: both sides powered on
01: N side powered down
10: P side powered down
11: both sides powered down
Bypass P/N InBuf separately.
00: bypass none sided
01: N side bypassed
10: P side bypassed
11: bypass both
Description
Reserved.
Temperature sensor chopping enable. Do not use chopping mode
together with the sequencer.
0: disable chopping mode
1: enable chopping mode
Temperature sensor power down.
0: power up temperature sensor
1: power down temperature sensor
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UG-498
Reset RW
0x000F RW
0x00 RW
0x00 RW
Reset Access
0x0 RW
0x3 RW
0x3 RW
Reset Access
0x0 R
0x0 RW
0x0 RW