Register Summary: Vdac; Register Details: Vdac - Analog Devices ADuCM320 Hardware Reference Manual

UG-498

REGISTER SUMMARY: VDAC

The CPU accesses the VDAC circuit over a die to die interface (D2D), which increases the execution times of ldr and str instructions. The
32-bit MMRs have addresses of 0x40086xxx and take 8 CPU cycles at 80 MHz to execute. The 16-bit MMRs have addresses of 0x40082xxx
and take 6 CPU cycles at 80 MHz to execute.
Table 36. VDAC Register Summary
Address Name
0x40082400 DAC0CON
0x40082404 DAC1CON
0x40082408 DAC2CON
0x4008240C DAC3CON
0x40082410 DAC4CON
0x40082414 DAC5CON
0x40082418 DAC6CON
0x4008241C DAC7CON
0x40086404 DAC0DAT
0x40086408 DAC1DAT
0x4008640C DAC2DAT
0x40086410 DAC3DAT
0x40086414 DAC4DAT
0x40086418 DAC5DAT
0x4008641C DAC6DAT
0x40086420 DAC7DAT

REGISTER DETAILS: VDAC

DAC0 Control Register
Address: 0x40082400, Reset: 0x0100, Name: DAC0CON
Table 37. Bit Descriptions for DAC0CON
Bits Bit Name
[15:9] RESERVED
8 PD
[7:5] RESERVED
4 EN
[3:2] RESERVED
[1:0] RN
DAC1 Control Register
Address: 0x40082404, Reset: 0x0100, Name: DAC1CON
Table 38. Bit Descriptions for DAC1CON
Bits Bit Name
[15:9] RESERVED
8 PD
Description
DAC0 control register
DAC1 control register
DAC2 control register
DAC3 control register
DAC4 control register
DAC5 control register
DAC6 control register
DAC7 control register
DAC0 data register
DAC1 data register
DAC2 data register
DAC3 data register
DAC4 data register
DAC5 data register
DAC6 data register
DAC7 data register
Description
Reserved.
DAC0 power down.
0: DAC0 is powered up
1: DAC0 is powered down and output is floating
Reserved.
DAC0 enable. Must be set to 1.
0: DAC disable. Clear DAC data immediately
1: DAC enable.
Reserved.
DAC0 reference selection. These bits set the DAC range. A write to these
bits has immediate effect on the DAC.
00: internal reference
01: reserved
10: reserved
11: AVDD/AGND
Description
Reserved.
DAC1 power down.
0: DAC1 is powered up
1: DAC1 is powered down and output is floating
Rev. C | Page 44 of 196
ADuCM320 Hardware Reference Manual
Reset RW
0x0100 RW
0x0100 RW
0x0100 RW
0x0100 RW
0x0100 RW
0x0100 RW
0x0100 RW
0x0100 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
0x00000000 RW
Reset Access
0x0 R
0x1 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x1 RW