System Exceptions And Peripheral Interrupts; Cortex-M3 And Fault Management - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

The ADuCM320 integrates an ARM Cortex-M3 processor, which supports several of system exceptions and interrupts generated by
peripherals. Table 53 lists the ARM Cortex-M3 processor system exceptions.
Table 53. System Exceptions
Number Type
1 Reset
2 NMI
3 Hard fault
4 Memory management
fault
5 Bus fault
6 Usage fault
7 to 10 Reserved
11 SVCall
12 Debug monitor
13 Reserved
14 PendSV
15 SYSTICK
The peripheral interrupts are controlled by the NVIC and are listed in Table 54. All interrupt sources can wake up the device from
Mode 1. Only a limited number of interrupts can wake up the processor from the low power modes (Mode 2 and Mode 3) as shown in
Table 54. When the device is woken up from Mode 2 or Mode 3, it returns to Mode 0. If the processor enters any power mode from Mode
1 to Mode 3 while the processor is in an interrupt handler, only an interrupt source with a higher priority than the current interrupt can
wake up the device (higher value in IPRx registers).
Two steps are usually required to configure an interrupt
•
Configuring a peripheral to generate an interrupt request to the NVIC.
•
Configuring the NVIC for that peripheral request.
Table 54. Interrupt Vector Table
Position No. Vector
0 Wake-up timer
1 External Interrupt 0
2 External Interrupt 1
3 External Interrupt 2
4 Reserved
5 External Interrupt 4
6 External Interrupt 5
7 Reserved
8 External Interrupt 7
9 External Interrupt 8
10 Watchdog timer
11 Reserved
12 Reserved
13 LV Die Interrupt 0
14 MDIO
15 GP Timer 0
16 GP Timer 1
17 Flash controller
18 UART
19 SPI0
Priority Description
−3 (highest) Any reset.
−2 Nonmaskable interrupt not connected on the ADuCM320.
−1 All fault conditions if the corresponding fault handler is not enabled.
Programmable Memory management fault; access to invalid locations.
Programmable Prefetch fault, memory access fault, data abort, and other address/memory related faults.
Programmable Same as undefined instruction executed or invalid state transition attempt.
N/A
Programmable System service call with SVC instruction. Used for system function calls.
Programmable Debug monitor (breakpoint, watchpoint, or external debug requests).
N/A
Programmable Pendable request for system service. Used for queuing system calls until other tasks
and interrupts are serviced.
Programmable System tick timer.
Wake Up Processor from Mode 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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Wake Up Processor from Mode 2 or Mode 3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
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