Dma Transfer Types (Chnl_Cfg[2:0]); Changes To Table 75 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
Bits Name
[25:24] SRC_SIZE
[23:18] RESERVED
[17:14] R_POWER
[13:4] N_MINUS_1
3 RESERVED
[2:0] CYCLE_CTRL
During the DMA transfer process, but before arbitration, CHNL_CFG is written back to system memory with the N_MINUS_1 field
changed to reflect the number of transfers yet to be completed.
When the DMA cycle is complete, the CYCLE_CTRL bits are made invalid to indicate the completion of the transfer.

DMA TRANSFER TYPES (CHNL_CFG[2:0])

The DMA controller supports five types of DMA transfers. The various types are selected by programming the appropriate values into the
CYCLE_CTRL bits (Bits[2:0]) in the CHNL_CFG location of the control data structure.
Invalid (CHNL_CFG[2:0] = 000)
This means no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets the cycle type to invalid to
prevent it from repeating the same DMA cycle.
Basic (CHNL_ CFG[2:0] = 001)
In this mode, the controller can be configured to use either the primary or alternate data structure. The peripheral must present a request
for every data transfer. After the channel is enabled, when the controller receives a request, it performs the following operations:
1. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3.
2. The controller arbitrates
a. If a higher priority channel is requesting service, then the controller services that channel.
b. If the peripheral or software signals a request to the controller, then it continues at Step 1.
3. At the end of the transfer, the controller generates the corresponding DMA channel interrupt in the NVIC
Description
Size of the source data.
00: byte.
01: half word.
10: word.
11: reserved.
Undefined. Write as 0.
Set these bits to control how many DMA transfers can occur before the controller re-arbitrates. Must be set
to 0000 for all DMA transfers involving peripherals. Note that the operation of the DMA is indeterminate
if a value other than 0000 is programmed in this location for DMA transfers involving peripherals.
The number of configured transfers minus 1 for that channel. The 10-bit value indicates the number
of DMA transfers (not the total number of bytes) minus one. The possible values are
0x000: 1 DMA transfer
0x001: 2 DMA transfers
0x002: 3 DMA transfers
...
0x3FF: 1024 DMA transfers.
Undefined. Write as 0.
The transfer types of the DMA cycle.
000: stop (invalid)
001: basic
010: autorequest
011: ping-pong
100: memory scatter-gather primary
101: memory scatter-gather alternate
110: peripheral scatter-gather primary
111: peripheral scatter-gather alternate
Rev. C | Page 64 of 196
ADuCM320 Hardware Reference Manual