Vdacs; Vdac Features; Vdac Block Diagram; Vdac Overview - Analog Devices ADuCM320 Hardware Reference Manual

ADuCM320 Hardware Reference Manual

VDACs

VDAC FEATURES

The ADuCM320 has eight VDACs. The specified load resistance is greater than 5 kΩ, and the specified capacitance is less than 100 pF.

VDAC BLOCK DIAGRAM

VDAC OVERVIEW

The ADuCM320 has eight VDACs specified to drive 5 kΩ load, 500 μA maximum.
The VDACs can select from two reference sources:

0 V to internal reference, V

0 V to AV (3.3 V)
DD

VDAC OPERATION

The DAC is configurable through a control register and a data register. The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, as shown in Figure 11.
The linearity specification of the DAC when driving a 5 kΩ resistive load to ground is guaranteed through the full transfer function
except for Code 0 to Code 100; in 0-to-AV
Linearity degradation near ground and AV
(neglecting offset and gain error) is shown in Figure 12.
The dotted line in Figure 12 indicates the ideal transfer function. The solid line represents what the transfer function may look like with
endpoint nonlinearities due to saturation of the output amplifier. Figure 12 represents a transfer function in 0-to-AV
to-V mode, the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line all the way to
REF
the end, showing no signs of endpoint linearity errors.
V
STRING DAC
REF
Figure 11. Output Mode Capacitor Load ≤ 100 pF
(0 V to 2.5 V)
REF
mode, the linearity specification is also not guaranteed for Code 3995 to Code 4095.
DD
is caused by saturation of the output amplifier; a general representation of its effects
DD
AVDD
0x00000000
Figure 12. DAC Endpoint Nonlinearities Due to Amplifier Saturation
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DAC_BUF
0x0FFF0000
DACOUT
mode only. In 0-
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UG-498