Analog Devices ADuCM320 Hardware Reference Manual page 122

UG-498
Master and Slave FIFO Status Register
Address: 0x4000344C, Reset: 0x0000, Name: I2C1FSTA
Table 175. Bit Descriptions for I2C1FSTA
Bits Bit Name
[15:10] RESERVED
9 MFLUSH
8 SFLUSH
[7:6] MRXFSTA
[5:4] MTXFSTA
[3:2] SRXFSTA
[1:0] STXFSTA
Master and Slave Shared Control Register
Address: 0x40003450, Reset: 0x0000, Name: I2C1SHCON
Table 176. Bit Descriptions for I2C1SHCON
Bits Bit Name
[15:1] RESERVED
0 RESET
Description
Reserved.
Flush the master transmit FIFO.
0: clearing to 0 has no effect.
1: set to 1 to flush the master transmit FIFO. The master transmit FIFO must
be flushed if arbitration is lost or a slave responds with a NACK.
Flush the slave transmit FIFO.
0: clearing to 0 has no effect.
1: set to 1 to flush the slave transmit FIFO.
Master receive FIFO status. The status is a count of the number of bytes in
a FIFO.
00: FIFO empty
01: 1 bytes in the FIFO
10: 2 bytes in the FIFO
11: reserved
Master transmit FIFO status. The status is a count of the number of bytes in
a FIFO.
00: FIFO empty
01: 1 bytes in the FIFO
10: 2 bytes in the FIFO
11: reserved
Slave receive FIFO status. The status is a count of the number of bytes in a
FIFO.
00: FIFO empty
01: 1 bytes in the FIFO
10: 2 bytes in the FIFO
11: reserved
Slave transmit FIFO status. The status is a count of the number of bytes in a
FIFO.
00: FIFO empty
01: 1 bytes in the FIFO
10: 2 bytes in the FIFO
11: reserved
Description
Reserved.
Write a 1 to this bit to reset the I
Setting this bit resets the LINEBUSY status bit.
Rev. C | Page 122 of 196
ADuCM320 Hardware Reference Manual
C start and stop detection circuits.
2
Reset Access
0x0 RW
0x0 W
0x0 W
0x0 R
0x0 R
0x0 R
0x0 R
Reset Access
0x0000 RW
0x0 W