Analog Devices ADuCM320 Hardware Reference Manual page 142

UG-498
Bits Bit Name
4 EDMAT
3 EDSSI
2 ELSI
1 ETBEI
0 ERBFI
Interrupt Identification Register
Address: 0x40005008, Reset: 0x0001, Name: COMIIR
Table 198. Bit Descriptions for COMIIR
Bits Bit Name
[15:3] RESERVED
[2:1] STA
0 NIRQ
Line Control Register
Address: 0x4000500C, Reset: 0x0000, Name: COMLCR
Table 199. Bit Descriptions for COMLCR
Bits Bit Name
[15:7] RESERVED
6 BRK
5 SP
4 EPS
Description
DMA requests in transmit mode.
0: DMA requests are disabled
1: DMA requests are enabled
Modem status interrupt. Interrupt is generated when any of COMMSR[3:0]
are set.
0: interrupt disabled
1: interrupt enabled
Rx status interrupt.
0: interrupt disabled
1: interrupt enabled
Transmit buffer empty interrupt.
0: interrupt disabled
1: interrupt enabled
Receive buffer full interrupt.
0: interrupt disabled
1: interrupt enabled
Description
Reserved.
Interrupt status. When NIRQ is low (active low), this indicates an interrupt
and the STA bit decoding below is used.
00: modem status interrupt (read COMMSR to clear)
01: transmit buffer empty interrupt (write to COMTX or read COMIIR to clear)
10: receive buffer full interrupt (read COMRX to clear)
11: receive line status interrupt (read COMLSR to clear)
Interrupt flag.
0: interrupt occurred. Source of interrupt indicated in the STA bits.
1: no interrupt occurred.
Description
Reserved.
Set break.
0: force TxD to 0
1: normal TxD operation
Stick parity. Used to force parity to defined values. When set, the parity is
based on the following bit settings :
EPS = 1 and PEN = 1, parity is forced to 0
EPS = 0 and PEN = 1, parity is forced to 1
EPS = X and PEN = 0, no parity is transmitted
0: Parity is not forced based on EPS and PEN
1: Parity forced based on EPS and PEN
Parity select. This bit only has meaning if parity is enabled (PEN set).
0: odd parity is transmitted and checked
1: even parity is transmitted and checked
Rev. C | Page 142 of 196
ADuCM320 Hardware Reference Manual
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW
0x0 RW
Reset Access
0x0 R
0x0 RC
0x1 RC
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW