Changes To Table 182 - Analog Devices ADuCM320 Hardware Reference Manual

UG-498
Baud Rate Selection Register
Address: 0x4002C00C, Reset: 0x0000, Name: SPI0DIV
Table 182. Bit Descriptions for SPI0DIV
Bits Bit Name
[15:9] RESERVED
8 CSIRQ_EN
7 BCRST
6 RESERVED
[5:0] DIV
SPI Configuration Register
Address: 0x4002C010, Reset: 0x0000, Name: SPI0CON
Table 183. Bit Descriptions for SPI0CON
Bits Bit Name
[15:14] MOD
13 TFLUSH
12 RFLUSH
11 CON
Description
Reserved.
Enable interrupt on every CS edge in CONT mode. If this bit is set and the
SPI module is in continuous mode, any edge on CS generates an interrupt
and the corresponding status bits (CSRSG, CSFLG) are asserted. If this bit is
clear, no interrupt is generated. This bit has no effect if the SPI is not in
continuous mode.
Reset mode for CSERR. If this bit is set, the bit counter is reset after a CS
error condition and the Cortex is expected to clear the SPI enable bit. If
this bit is clear, the bit counter continues from where it stopped. SPI can
receive the remaining bits when CS gets asserted and Cortex has to ignore
the CSERR interrupt. However, it is strongly recommended to set this bit
for a graceful recovery after a CS error.
Reserved.
SPI clock divider. DIV is the factor used to divide UCLK to generate the
serial clock.
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in
a transfer. For DMA Rx transfer, these bits should be 00.
00: Tx interrupt occurs when 1 byte has been transferred. Rx interrupt
occurs when 1 or more bytes have been received into the FIFO.
01: Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt
occurs when 2 or more bytes have been received into the FIFO.
10: Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt
occurs when 3 or more bytes have been received into the FIFO.
11: Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt
occurs when the Rx FIFO is full, or 4 bytes present.
SPI Tx FIFO flush enable.
0: clear this bit to disable Tx FIFO flushing.
1: set this bit to flush the Tx FIFO. This bit does not clear itself and should
be toggled if a single flush is required. If this bit is left high, then either the
last transmitted value or 0x00 is transmitted depending on the ZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
SPI Rx FIFO flush enable.
0: clear this bit to disable Rx FIFO flushing.
1: set this bit to flush the Rx FIFO. This bit does not clear itself and should
be toggled if a single flush is required. If this bit is set, all incoming data is
ignored and no interrupts are generated. If set and TIM = 0, a read of the
Rx FIFO initiates a transfer.
Continuous transfer enable.
0: DIS. Cleared by user to disable continuous transfer. Each transfer
consists of a single 8-bit serial transfer. If valid data exists in the SPI0TX
register, a new transfer is initiated after a stall period of 1 serial clock cycle.
1: EN. Set by user to enable continuous transfer. In master mode, the
transfer continues until no valid data is available in the Tx register. CS is
asserted and remains asserted for the duration of each 8-bit serial transfer
until Tx is empty.
Rev. C | Page 130 of 196
ADuCM320 Hardware Reference Manual
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 R/W
0x0 RW
Reset Access
0x0 RW
0x0 RW
0x0 RW
0x0 RW