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Addr.
Register Name
Port A Data Register
$0000
Port B Data Register
$0001
Port C Data Register
$0002
Port D Data Register
$0003
Data Direction Register A
$0004
(DDRA)
Data Direction Register B
$0005
(DDRB)
Data Direction Register C
$0006
(DDRC)
Data Direction Register D
$0007
(DDRD)
Port E Data Register
$0008
Port F Data Register
$0009
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 11)
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Bit 7
Read:
PTA7
Write:
(PTA)
Reset:
Read:
PTB7
Write:
(PTB)
Reset:
Read:
0
Write:
(PTC)
Reset:
Read:
PTD7
Write:
(PTD)
Reset:
Read:
DDRA7
Write:
Reset:
0
Read:
DDRB7
Write:
Reset:
0
Read:
MCLKEN
Write:
Reset:
0
Read:
DDRD7
Write:
Reset:
0
Read:
PTE7
Write:
(PTE)
Reset:
Read:
PTF7
Write:
(PTF)
Reset:
= Unimplemented
6
5
4
PTA6
PTA5
PTA4
Unaffected by reset
PTB6
PTB5
PTB4
Unaffected by reset
0
PTC5
PTC4
Unaffected by reset
PTD6
PTD5
PTD4
Unaffected by reset
DDRA6
DDRA5
DDRA4
0
0
0
DDRB6
DDRB5
DDRB4
0
0
0
0
DDRC5
DDRC4
0
0
0
DDRD6
DDRD5
DDRD4
0
0
0
PTE6
PTE5
PTE4
Unaffected by reset
PTF6
PTF5
PTF4
Unaffected by reset
Memory Map
Input/Output (I/O) Section
3
2
1
PTA3
PTA2
PTA1
PTB3
PTB2
PTB1
PTC3
PTC2
PTC1
PTD3
PTD2
PTD1
DDRA3
DDRA2
DDRA1
0
0
0
DDRB3
DDRB2
DDRB1
0
0
0
DDRC3
DDRC2
DDRC1
0
0
0
DDRD3
DDRD2
DDRD1
0
0
0
PTE3
PTE2
PTE1
PTF3
PTF2
PTF1
R
= Reserved
Technical Data
Memory Map
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
0
DDRB0
0
DDRC0
0
DDRD0
0
PTE0
PTF0
45
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