Phase-Locked Loop (Pll) Circuit; Pll Circuits - Motorola MC68HC908AB32 Technical Data Manual

9.4.2 Phase-Locked Loop (PLL) Circuit

9.4.2.1 PLL Circuits

MC68HC908AB32 Rev. 1.0
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MOTOROLA
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
The PLL consists of the following circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
frequency, f , (4.9152MHz) times a linear factor L, or (L)f
NOM
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency f
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f
RDV
The VCO's output clock, CGMVCLK, running at a frequency f
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor N. The divider's output is the VCO
feedback clock, CGMVDV, running at a frequency f
9.4.2.4 Programming the PLL
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
Clock Generator Module (CGM)
is equal to the nominal center-of-range
VRS
, and is fed to the PLL through a
RCLK
= f .
RCLK
for more information).
Clock Generator Module (CGM)
Functional Description
VRS
NOM
VCLK
= f /N. (See
VDV VCLK
Technical Data
.
.
, is fed
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