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Low-Voltage Inhibit (LVI)
21.5 LVI Status Register (LVISR)
21.6 LVI Interrupts
Technical Data
362
The LVI status register flags V
Address:
$FE0F
Bit 7
6
Read: LVIOUT
0
Write:
Reset:
0
0
= Unimplemented
Figure 21-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when V
voltage for 32 to 40 CGMXCLK cycles. (See
clears the LVIOUT bit.
Table 21-1. LVIOUT Bit Indication
At level:
V
> LVI
DD
TRIPR
< LVI
V
DD
TRIPF
< LVI
V
DD
TRIPF
< LVI
V
DD
TRIPF
< V
< LVI
LVI
TRIPF
DD
The LVI module does not generate interrupt requests.
Low-Voltage Inhibit (LVI)
voltages below the LVI
DD
5
4
0
0
0
0
V
DD
For number of CGMXCLK
cycles:
Any
< 32 CGMXCLK cycles
32 to 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
TRIPR
level
TRIPF
3
2
1
0
0
0
0
0
0
falls below the LVI
DD
Table 21-1
.) Reset
LVIOUT
0
0
0 or 1
1
Previous value
MC68HC908AB32
—
MOTOROLA
.
Bit 0
0
0
TRIPF
Rev. 1.0
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