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Clock Generator Module (CGM)
Addr.
Register Name
PLL Control Register
$001C
(PCTL)
PLL Bandwidth Control
$001D
Register
(PBWC)
PLL Programming
$001E
Register
(PPG)
9.4.1 Crystal Oscillator Circuit
Technical Data
134
Bit 7
6
Read:
PLLF
PLLIE
Write:
Reset:
0
0
Read:
LOCK
AUTO
Write:
Reset:
0
0
Read:
MUL7
MUL6
Write:
Reset:
0
1
= Unimplemented
Figure 9-2. CGM I/O Register Summary
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock can also feed the OSC1 pin of the crystal
oscillator circuit. For this configuration, the external clock should be
connected to the OSC1 pin and the OSC2 pin allowed to float.
Clock Generator Module (CGM)
5
4
3
1
PLLON
BCS
1
0
1
0
ACQ
XLD
0
0
0
MUL5
MUL4
VRS7
1
0
0
2
1
Bit 0
1
1
1
1
1
1
0
0
0
0
0
0
VRS6
VRS5
VRS4
1
1
0
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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