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21.4.1 Polled LVI Operation
21.4.2 Forced Reset Operation
21.4.3 False Reset Protection
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Address:
$FE0F
Bit 7
6
Read: LVIOUT
0
Write:
Reset:
0
0
= Unimplemented
Figure 21-2. LVI I/O Register Summary
In applications that can operate at V
software can monitor V
register 1, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls below the LVI
more consecutive CPU cycles. In configuration register 1, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
The V
pin level is digitally filtered to reduce false resets due to power
DD
supply noise. In order for the LVI module to reset the MCU, V
remain at or below the LVI
cycles. V
must be above LVI
DD
MCU out of reset.
Low-Voltage Inhibit (LVI)
5
4
0
0
0
0
DD
by polling the LVIOUT bit. In configuration
DD
to remain above the LVI
DD
level and remains at or below that level for 9 or
TRIPF
level for 9 or more consecutive CPU
TRIPF
for only one CPU cycle to bring the
TRIPR
Low-Voltage Inhibit (LVI)
Functional Description
3
2
1
0
0
0
0
0
0
levels below the LVI
TRIPF
Bit 0
0
0
level,
TRIPF
level,
DD
must
DD
Technical Data
361
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