Table of Contents
Advertisement
Source
Form
LSR opr
LSRA
LSR X
Logical Shift Right
LSR opr ,X
LSR ,X
LSR opr ,SP
MOV opr,opr
MOV opr, X+
Move
MOV # opr,opr
MOV X+ ,opr
MUL
Unsigned multiply
NEG opr
NEGA
NEGX
Negate (Two's Complement)
NEG opr ,X
NEG ,X
NEG opr ,SP
NOP
No Operation
NSA
Nibble Swap A
ORA # opr
ORA opr
ORA opr
ORA opr ,X
Inclusive OR A and M
ORA opr ,X
ORA ,X
ORA opr ,SP
ORA opr ,SP
PSHA
Push A onto Stack
PSHH
Push H onto Stack
PSHX
Push X onto Stack
PULA
Pull A from Stack
PULH
Pull H from Stack
PULX
Pull X from Stack
ROL opr
ROLA
ROLX
Rotate Left through Carry
ROL opr ,X
ROL ,X
ROL opr ,SP
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
Table 7-1. Instruction Set Summary (Continued)
Operation
H:X ← (H:X) + 1 (IX+D, DIX+)
Central Processor Unit (CPU)
Description
0
C
b7
b0
← (M)
(M)
Destination
Source
X:A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
None
A ← (A[3:0]:A[7:4])
A ← (A) | (M)
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
C
b7
b0
Central Processor Unit (CPU)
Effect on
CCR
V H I N Z C
DIR
INH
INH
– – 0
IX1
IX
SP1
DD
DIX+
0 – –
–
IMD
IX+D
– 0 – – – 0 INH
DIR
INH
INH
– –
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
IMM
DIR
EXT
IX2
0 – –
–
IX1
IX
SP1
SP2
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
DIR
INH
INH
– –
IX1
IX
SP1
Opcode Map
34
dd
4
44
1
54
1
64
ff
4
74
3
9E64
ff
5
4E
dd dd
5
5E
dd
4
6E
ii dd
4
7E
dd
4
42
5
30
dd
4
40
1
50
1
60
ff
4
70
3
9E60
ff
5
9D
1
62
3
AA
ii
2
BA
dd
3
CA
hh ll
4
DA
ee ff
4
EA
ff
3
FA
2
9EEA
ff
4
9EDA
ee ff
5
87
2
8B
2
89
2
86
2
8A
2
88
2
39
dd
4
49
1
59
1
69
ff
4
79
3
9E69
ff
5
Technical Data
103
Advertisement
Table of Contents
