Sim Bus Clock Control And Generation - Motorola MC68HC908AB32 Technical Data Manual

System Integration Module (SIM)
Addr. Register Name
SIM Break Status Register
$FE00
(SBSR)
Note: Writing a logic 0 clears SBSW.
SIM Reset Status Register
$FE01
(SRSR)
SIM Break Flag Control
$FE03 Register
(SBFCR)

8.3 SIM Bus Clock Control and Generation

OSC1
CGMVCLK
PLL
Technical Data
112
Bit 7 6
Read:
R R
Write:
Reset: 0 0
Read: POR PIN
Write:
POR: 1 0
Read:
BCFE R
Write:
Reset: 0
= Unimplemented
Figure 8-2. SIM I/O Register Summary
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip PLL.
See Section 9. Clock Generator Module
CLOCK
÷
SELECT
2
CIRCUIT
BCS
PTC3
MONITOR MODE
USER MODE
CGM
Figure 8-3. CGM Clock Signals
System Integration Module (SIM)
5 4 3
R R R
0 0 0
COP ILOP ILAD
0 0 0
R R R
R
Figure
(CGM).
CGMXCLK
A
CGMOUT
B S *
*
When S = 1,
CGMOUT = B
2 1 Bit 0
SBSW
R R
Note
0 0 0
0 LVI 0
0 0 0
R R R
= Reserved
8-3. This clock can come
SIM COUNTER
÷
BUS CLOCK
2
GENERATORS
SIM
MC68HC908AB32 Rev. 1.0
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MOTOROLA