Data Strobe Control Of Data Bus In Master Mode - Motorola MC68824 User Manual

5.3.3 Data Transfer Acknowledge (DTACK)
OTACK is a bidirectional three-state signal which indicates that an asynchronous bus cycle may
be terminated. In the slave mode, this output indicates that the TBC has accepted data from the
host processor or placed data onto the bus for the host processor. In the master mode, this input
is monitored by the TBC to determine when to terminate a bus cycle. As long as OTACK remains
negated, the TBC will insert wait cycles into the bus cycle. When OTACK is asserted, the bus cycle
will be terminated.
5.3.4 ReadlWrite (RIW)
RIW is a bidirectional three-state signal that indicates the direction of the data transfer during a
bus cycle. The RIW pin is an input in the slave mode and an output in master mode. Thus, in the
slave mode, a high level indicates that a transfer is from the TBC onto the data bus, and a low
level indicates that a transfer is from the data bus into the TBC. In the master mode, a high level
indicates that a transfer is from the data bus into the TBC, and a low level indicates that a transfer
is from the TBC onto the data bus.
5.3.5 Upper Data Strobe (UDS/AO), Lower Data Strobe (LDS/DS)
These bidirectional three-state signals control the flow of data onto the data bus. UOS and LOS
are asserted by the TBC when operating in the master mode and by the host processor when
operating in slave mode. In the master mode, during any 16-bit bus cycle, UOS is asserted if data
is to be transferred over the data lines 08-015, and LOS is asserted if data is to be transferred
over data lines 00-07. For an 8-bit bus configuration, UOS functions as AO and LOS functions as
data strobe. AO is thus an extension of the lower address lines to provide the address of a byte
in the address map and is valid when A1-A31 are valid. OS is a data strobe used to enable external
data buffers and indicates that valid data is on the bus during a write cycle. In the slave mode,
UOS and LOS operate in conjunction with A 1, A2, and CS as indicated in 6.6 REGISTERS and
5.5.5 Chip Select (CS). Figure 5-2 shows the various signal combinations and when data is valid
on the data lines.
5.3.6 Address Strobe (AS)
This bidirectional three-state signal indicates that there is a valid address on the address bus. It
is an output when the TBC is in master mode and has control of the bus. AS is an input during
UDS LOS
RIW
08-015
00-07
16-BIT TRANSFER
HIGH HIGH X NO VALID DATA NO VALID DATA
LOW LOW X
VALID DATA 8-15 VALID DATA 0-7
HIGH LOW LOW NO VALID DATA VALID DATA 0-7
HIGH LOW HIGH X
VALID DATA 0-7
LOW
HIGH
LOW
VALID DATA 8-15 NO VALID DATA
LOW HIGH HIGH VALID DATA 8-15
X
8-BIT TRANSFER
X
LOW
LOW NO VALID DATA VALID DATA 0-7
X LOW HIGH X
VALID DATA 0-7
X HIGH X NO VALID DATA
NO VALID DATA
x -
Don't Care
Figure 5-2. Data Strobe Control of Data Bus in Master Mode
MC68824 USER'S MANUAL
MOTOROLA
5-3
II