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NOTE:
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
MISO — Master In/Slave Out
The PTE5/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTE5/MISO pin is available for general-purpose
I/O. See
16.14.1 SPI Control
SS — Slave Select
The PTE4/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTE4/SS pin is available for general-purpose I/O. See
Control
Register. When the SPI is enabled as a slave, the DDRE4
bit in data direction register E (DDRE) has no effect on the PTE4/SS
pin.
TACH[1:0] — Timer A Channel I/O Bits
The PTE3/TACH1–PTE2/TACH0 pins are the TIMA input
capture/output compare pins. The edge/level select bits,
ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0
pins are timer channel I/O pins or general-purpose I/O pins. See
11.10.4 TIMA Channel Status and Control
RxD — SCI Receive Data Input
The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See
SCI Control Register
TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See
15.9.1 SCI Control Register
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SPI module, TIMA, and SCI
module. However, the DDRE bits always determine whether reading
port E returns the states of the latches or the states of the pins. See
Table
17-6.
Input/Output (I/O) Ports
Register.
1.
1.
Input/Output (I/O) Ports
Port E
16.14.1 SPI
Registers.
15.9.1
Technical Data
327
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