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Memory Map
Addr.
Register Name
PLL Programming
$001E
Register
(PPG)
Configuration Register 1
$001F
(CONFIG1)
† One-time writable register after each reset.
Timer A Status and
$0020
Control Register
(TASC)
Keyboard Interrupt Enable
$0021
Register
(KBIER)
Timer A Counter
$0022
Register High
(TACNTH)
Timer A Counter
$0023
Register Low
(TACNTL)
Timer A Counter Modulo
$0024
Register High
(TAMODH)
Timer A Counter Modulo
$0025
Register Low
(TAMODL)
Timer A Channel 0 Status
$0026
and Control Register
(TASC0)
Timer A Channel 0
$0027
Register High
(TACH0H)
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 11)
Technical Data
48
Bit 7
6
Read:
MUL7
MUL6
Write:
Reset:
0
1
Read:
LVISTOP
R
Write:
†
Reset:
0
0
Read:
TOF
TOIE
Write:
0
Reset:
0
0
Read:
0
0
Write:
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
0
0
Read:
Bit 7
6
Write:
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
1
1
Read:
Bit 7
6
Write:
Reset:
1
1
Read:
CH0F
CH0IE
Write:
0
Reset:
0
0
Read:
Bit 15
14
Write:
Reset:
= Unimplemented
Memory Map
5
4
3
MUL5
MUL4
VRS7
1
0
0
LVIRSTD LVIPWRD SSREC
0
0
0
0
0
TSTOP
TRST
1
0
0
0
KBIE4
KBIE3
0
0
0
13
12
11
0
0
0
5
4
3
0
0
0
13
12
11
1
1
1
5
4
3
1
1
1
MS0B
MS0A
ELS0B
0
0
0
13
12
11
Indeterminate after reset
R
2
1
Bit 0
VRS6
VRS5
VRS4
1
1
0
COPRS
STOP
COPD
0
0
0
PS2
PS1
PS0
0
0
0
KBIE2
KBIE1
KBIE0
0
0
0
10
9
Bit 8
0
0
0
2
1
Bit 0
0
0
0
10
9
Bit 8
1
1
1
2
1
Bit 0
1
1
1
ELS0A
TOV0
CH0MAX
0
0
0
10
9
Bit 8
= Reserved
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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