Motorola MC68HC908AB32 Technical Data Manual page 105

Source
Form
SUB # opr
SUB opr
SUB opr
SUB opr ,X
Subtract
SUB opr ,X
SUB ,X
SUB opr ,SP
SUB opr ,SP
SWI Software Interrupt
TAP Transfer A to CCR
TAX Transfer A to X
TPA Transfer CCR to A
TST opr
TSTA
TSTX
Test for Negative or Zero
TST opr ,X
TST ,X
TST opr ,SP
TSX Transfer SP to H:X
TXA Transfer X to A
TXS Transfer H:X to SP
MC68HC908AB32 Rev. 1.0
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MOTOROLA
Table 7-1. Instruction Set Summary (Continued)
Operation
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
(A) – $00 or (X) – $00 or (M) – $00
Central Processor Unit (CPU)
Description
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
CCR ← (A)
X ← (A)
A ← (CCR)
H:X ← (SP) + 1
A ← (X)
(SP) ← (H:X) – 1
Central Processor Unit (CPU)
Effect on
CCR
V H I N Z C
IMM
DIR
EXT
IX2
– –
IX1
IX
SP1
SP2
– – 1 – – – INH
INH
– – – – – – INH
– – – – – – INH
DIR
INH
INH
0 – – –
IX1
IX
SP1
– – – – – – INH
– – – – – – INH
– – – – – – INH
Opcode Map
A0 ii 2
B0 dd 3
C0 hh ll 4
D0 ee ff 4
E0 ff 3
F0 2
9EE0 ff 4
9ED0 ee ff 5
83 9
84 2
97 1
85 1
3D dd 3
4D 1
5D 1
6D ff 3
7D 2
9E6D ff 4
95 2
9F 1
94 2
Technical Data
105