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14.4.5 Accuracy and Precision
14.5 Interrupts
14.6 Low-Power Modes
14.6.1 Wait Mode
14.6.2 Stop Mode
14.7 I/O Signals
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
The conversion process is monotonic and has no missing codes.
When the AIEN bit is set, the ADC module is capable of generating
CPU interrupts after each ADC conversion. A CPU interrupt is
generated if the COCO bit is at logic 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
The WAIT and STOP instruction can put the MCU in low power-
consumption standby modes.
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH[4:0] bits in the ADC status and
control register before executing the WAIT instruction.
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when
the MCU exits stop mode after an external interrupt. Allow one
conversion cycle to stabilize the analog circuitry.
The ADC module has eight pins shared with port B,
PTB7/ATD7–PTB0/ATD0.
Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
Technical Data
Interrupts
233
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