Table of Contents
Advertisement
14.8.2 ADC Data Register (ADR)
14.8.3 ADC Clock Register (ADCLK)
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
One 8-bit result register, ADC data register (ADR), is provided. This
register is updated each time an ADC conversion completes.
Address:
$0039
Bit 7
6
Read:
AD7
AD6
Write:
Reset:
0
0
= Unimplemented
Figure 14-4. ADC Data Register (ADR)
The ADC clock register (ADCLK) selects the clock frequency for the
ADC.
Address:
$003A
Bit 7
6
Read:
ADIV2
ADIV1
Write:
Reset:
0
0
= Unimplemented
Figure 14-5. ADC Clock Register (ADCLK)
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV[2:0] form a 3-bit field which selects the divide ratio used by the
ADC to generate the internal ADC clock.
available clock configurations. The ADC clock should be set to
approximately 1 MHz.
Analog-to-Digital Converter (ADC)
Analog-to-Digital Converter (ADC)
5
4
3
AD5
AD4
AD3
0
0
0
5
4
3
0
ADIV0
ADICLK
0
0
0
I/O Registers
2
1
AD2
AD1
0
0
2
1
0
0
0
0
Table 14-2
shows the
Technical Data
Bit 0
AD0
0
Bit 0
0
0
237
Advertisement
Table of Contents
