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Freescale Semiconductor, Inc.
Asynchronous HDLC
has the highest priority. The rest of the frame is lost and other errors are not checked in that
frame. The receiver then searches for the next frame once CD is reasserted.
Abort Sequence
An abort sequence is detected by the ASYNC HDLC controller when the ABORT sequence
is received (0x7d followed by 0x7e). When this error occurs, the channel closes the buffer
(if it was already open) by setting the Rx Abort Sequence (AB) bit in the BD and sets the
RXF bit in the SCC Event Register. The CRC error status condition is not checked on abort-
ed frames. If the ABORT sequence was received and no frame was currently being re-
ceived, the next BD will be opened and then closed with the AB bit set.
CRC Error
When this error occurs, the channel writes the received CRC (Cyclic Redundancy Check)
to the data buffer, closes the buffer, sets the CR bit in the BD, and sets the RXF bit in the
SCC Event Register. After receiving a signal unit with a CRC error, the receiver prepares to
receive the next frame.
Break Sequence Received
This occurs when the UART receiver detects the first character of a break sequence (one or
more all-zero characters). When this error occurs, the channel closes the buffer (if it was al-
ready open) by setting the Rx Break Sequence (BRK) bit in the BD, and sets the RXF bit in
the SCC Event Register. The CRC error status condition is not checked. If the Break se-
quence was received and no frame was currently being received, the next BD will be opened
and then closed with the BRK bit set.
6 Registers
6.1 ASYNC HDLC Event Register
The SCCE register for an SCC is called the ASYNC HDLC Event Register when the SCC is
operating in Asynchronous HDLC mode. The ASYNC HDLC Event Register is a 16-bit reg-
ister which is used to report events recognized by the ASYNC HDLC channel and generate
interrupts. Upon recognition of an event, the ASYNC HDLC controller will set the corre-
sponding bit in the ASYNC HDLC event register. Interrupts generated by this register may
be masked by the ASYNC HDLC mask register.
The ASYNC HDLC event register is a memory-mapped register that may be read at any
time. A bit is cleared by writing a one (writing a zero does not affect a bit's value). More than
one bit may be cleared at a time. All unmasked bits must be cleared before the CP will clear
the internal interrupt request. This register is cleared at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
GLr
GLt
-
IDL
-
TXE
RXF
BSY
TXB
RXB
MOTOROLA
14
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