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Timer Interface Module A (TIMA)
11.10.5 TIMA Channel Registers
Technical Data
192
OVERFLOW
PERIOD
TACHx
OUTPUT
COMPARE
CHxMAX
Figure 11-13. CHxMAX Latency
These read/write registers contain the captured TIMA counter value of
the input capture function or the output compare value of the output
compare function. The state of the TIMA channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIMA channel x registers (TACHxH) inhibits input captures until the low
byte (TACHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIMA channel x registers (TACHxH) inhibits output compares until
the low byte (TACHxL) is written.
Address:
$0027
Bit 7
6
Read:
Bit 15
14
Write:
Reset:
Figure 11-14. TIMA Channel 0 Register High (TACH0H)
Address:
$0028
Bit 7
6
Read:
Bit 7
6
Write:
Reset:
Figure 11-15. TIMA Channel 0 Register Low (TACH0L)
Timer Interface Module A (TIMA)
OVERFLOW
OVERFLOW
OUTPUT
OUTPUT
COMPARE
COMPARE
5
4
3
13
12
11
Indeterminate after reset
5
4
3
5
4
3
Indeterminate after reset
OVERFLOW
OVERFLOW
OUTPUT
COMPARE
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
2
1
Bit 0
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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