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Central Processor Unit (CPU)
Technical Data
94
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
6
Read:
V
1
Write:
Reset:
X
1
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction uses
the states of the H and C flags to determine the appropriate correction
factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
Central Processor Unit (CPU)
5
4
3
1
H
I
1
X
1
MC68HC908AB32
2
1
Bit 0
N
Z
C
X
X
X
Rev. 1.0
—
MOTOROLA
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