Motorola MC68HC908AB32 Manuals

Manuals and User Guides for Motorola MC68HC908AB32. We have 1 Motorola MC68HC908AB32 manual available for free PDF download: Technical Data Manual

Motorola MC68HC908AB32 Technical Data Manual

Motorola MC68HC908AB32 Technical Data Manual (392 pages)

HCMOS Microcontroller Unit  
Brand: Motorola | Category: Controller | Size: 3.8 MB
Table of contents
Table Of Contents3................................................................................................................................................................
Introduction30................................................................................................................................................................
Mcu Block Diagram31................................................................................................................................................................
Mc68hc908ab32 Block Diagram32................................................................................................................................................................
Pin Assignments33................................................................................................................................................................
Pin Functions34................................................................................................................................................................
Oscillator Pins (osc1 And Osc2)35................................................................................................................................................................
Adc Voltage Reference Pin (v Refh )36................................................................................................................................................................
Port D I/o Pins (ptd7–ptd0)37................................................................................................................................................................
I/o Pin Summary38................................................................................................................................................................
Signal Name Conventions40................................................................................................................................................................
Section 2. Memory Map41................................................................................................................................................................
Reserved Memory Locations42................................................................................................................................................................
Memory Map43................................................................................................................................................................
Control, Status, And Data Registers45................................................................................................................................................................
Vector Addresses56................................................................................................................................................................
Section 3. Random-access Memory (ram)57................................................................................................................................................................
Section 4. Flash Memory59................................................................................................................................................................
Flash Control Register60................................................................................................................................................................
Flash Page Erase Operation61................................................................................................................................................................
Flash Mass Erase Operation62................................................................................................................................................................
Flash Program/read Operation63................................................................................................................................................................
Flash Block Protection64................................................................................................................................................................
Flash Programming Flowchart65................................................................................................................................................................
Flash Block Protect Register66................................................................................................................................................................
Wait Mode67................................................................................................................................................................
Section 5. Eeprom69................................................................................................................................................................
Features70................................................................................................................................................................
Functional Description71................................................................................................................................................................
Eeprom Timebase Requirements72................................................................................................................................................................
Eeprom Programming And Erasing73................................................................................................................................................................
Eeprom Programming74................................................................................................................................................................
Eeprom Erasing75................................................................................................................................................................
Low Power Modes76................................................................................................................................................................
Stop Mode77................................................................................................................................................................
Eeprom Program/erase Mode Select78................................................................................................................................................................
Eeprom Array Configuration Register79................................................................................................................................................................
Eeprom Non-volatile Register80................................................................................................................................................................
Eeprom Divider Register High (eedivh)81................................................................................................................................................................
Eeprom Timebase Divider Non-volatile Register82................................................................................................................................................................
Section 6. Configuration Register (config)85................................................................................................................................................................
Configuration Register 288................................................................................................................................................................
Section 7. Central Processor Unit (cpu)89................................................................................................................................................................
Accumulator91................................................................................................................................................................
Index Register92................................................................................................................................................................
Program Counter93................................................................................................................................................................
Condition Code Register (ccr)94................................................................................................................................................................
Arithmetic/logic Unit (alu)96................................................................................................................................................................
Instruction Set Summary98................................................................................................................................................................
Opcode Map107................................................................................................................................................................
Section 8. System Integration Module (sim)109................................................................................................................................................................
Sim Block Diagram111................................................................................................................................................................
Sim Bus Clock Control And Generation112................................................................................................................................................................
Bus Timing113................................................................................................................................................................
External Pin Reset114................................................................................................................................................................
Power-on Reset115................................................................................................................................................................
Computer Operating Properly (cop) Reset116................................................................................................................................................................
Illegal Opcode Reset117................................................................................................................................................................
Sim Counter During Power-on Reset118................................................................................................................................................................
Interrupts119................................................................................................................................................................
Hardware Interrupts120................................................................................................................................................................
Swi Instruction121................................................................................................................................................................
Reset123................................................................................................................................................................
Low-power Modes124................................................................................................................................................................
Stop Mode Entry Timing126................................................................................................................................................................
Sim Registers127................................................................................................................................................................
Sim Reset Status Register128................................................................................................................................................................
Sim Break Flag Control Register129................................................................................................................................................................
Section 9. Clock Generator Module (cgm)131................................................................................................................................................................
Crystal Oscillator Circuit134................................................................................................................................................................
Phase-locked Loop (pll) Circuit135................................................................................................................................................................
Acquisition And Tracking Modes136................................................................................................................................................................
Programming The Pll138................................................................................................................................................................
Special Programming Exceptions139................................................................................................................................................................
Base Clock Selector Circuit140................................................................................................................................................................
Cgm External Connections141................................................................................................................................................................
I/o Signals142................................................................................................................................................................
Crystal Output Frequency Signal (cgmxclk)143................................................................................................................................................................
Pll Control Register (pctl)144................................................................................................................................................................
Pll Bandwidth Control Register (pbwc)146................................................................................................................................................................
Pll Programming Register (ppg)148................................................................................................................................................................
Vco Frequency Multiplier (n) Selection149................................................................................................................................................................
Acquisition/lock Time Definitions152................................................................................................................................................................
Parametric Influences On Reaction Time153................................................................................................................................................................
Choosing A Filter Capacitor154................................................................................................................................................................
Reaction Time Calculation155................................................................................................................................................................
Section 10. Monitor Rom (mon)157................................................................................................................................................................
Monitor Mode Circuit159................................................................................................................................................................
Entering Monitor Mode160................................................................................................................................................................
Data Format161................................................................................................................................................................
Echoing162................................................................................................................................................................
Commands163................................................................................................................................................................
Write (write Memory) Command164................................................................................................................................................................
Iwrite (indexed Write) Command165................................................................................................................................................................
Baud Rate166................................................................................................................................................................
Security167................................................................................................................................................................
Extended Security168................................................................................................................................................................
Section 11. Timer Interface Module A (tima)169................................................................................................................................................................
Pin Name Conventions171................................................................................................................................................................
Tima Block Diagram172................................................................................................................................................................
Tima I/o Register Summary173................................................................................................................................................................
Input Capture174................................................................................................................................................................
Output Compare175................................................................................................................................................................
Buffered Output Compare176................................................................................................................................................................
Pulse Width Modulation (pwm)177................................................................................................................................................................
Unbuffered Pwm Signal Generation178................................................................................................................................................................
Buffered Pwm Signal Generation179................................................................................................................................................................
Pwm Initialization180................................................................................................................................................................
I/o Registers184................................................................................................................................................................
Tima Counter Registers186................................................................................................................................................................
Tima Counter Modulo Registers187................................................................................................................................................................
Tima Channel Status And Control Registers188................................................................................................................................................................
Tima Channel 2 Status And Control Register (tasc2)189................................................................................................................................................................
Mode, Edge, And Level Selection191................................................................................................................................................................
Tima Channel Registers192................................................................................................................................................................
Tima Channel 1 Register High (tach1h)193................................................................................................................................................................
Tima Channel 3 Register High (tach3h)194................................................................................................................................................................
Section 12. Timer Interface Module B (timb)195................................................................................................................................................................
Timb Block Diagram198................................................................................................................................................................
Timb I/o Register Summary199................................................................................................................................................................
Timb Counter Registers212................................................................................................................................................................
Timb Counter Modulo Registers213................................................................................................................................................................
Timb Channel Status And Control Registers214................................................................................................................................................................
Timb Channel 2 Status And Control Register (tbsc2)215................................................................................................................................................................
Timb Channel Registers218................................................................................................................................................................
Timb Channel 1 Register High (tbch1h)219................................................................................................................................................................
Timb Channel 3 Register High (tbch3h)220................................................................................................................................................................
Section 13. Programmable Interrupt Timer (pit)221................................................................................................................................................................
Pit Counter Prescaler223................................................................................................................................................................
Pit Counter Registers227................................................................................................................................................................
Pit Counter Modulo Registers228................................................................................................................................................................
Section 14. Analog-to-digital Converter (adc)229................................................................................................................................................................
Adc Port I/o Pins232................................................................................................................................................................
Accuracy And Precision233................................................................................................................................................................
Adc Status And Control Register (adscr)235................................................................................................................................................................
Mux Channel Select236................................................................................................................................................................
Adc Data Register (adr)237................................................................................................................................................................
Adc Clock Divide Ratio238................................................................................................................................................................
Module (sci)239................................................................................................................................................................
Sci Module Block Diagram243................................................................................................................................................................
Sci I/o Register Summary244................................................................................................................................................................
Sci Transmitter246................................................................................................................................................................
Character Length247................................................................................................................................................................
Break Characters248................................................................................................................................................................
Inversion Of Transmitted Output249................................................................................................................................................................
Receiver250................................................................................................................................................................
Sci Receiver Block Diagram251................................................................................................................................................................
Data Sampling252................................................................................................................................................................
Start Bit Verification253................................................................................................................................................................
Framing Errors254................................................................................................................................................................
Slow Data255................................................................................................................................................................
Fast Data256................................................................................................................................................................
Receiver Wakeup257................................................................................................................................................................
Receiver Interrupts258................................................................................................................................................................
Sci During Break Module Interrupts260................................................................................................................................................................
Sci Control Register 1 (scc1)262................................................................................................................................................................
Sci Control Register 2264................................................................................................................................................................
Sci Control Register 2 (scc2)265................................................................................................................................................................
Sci Control Register 3267................................................................................................................................................................
Sci Status Register 1269................................................................................................................................................................
Flag Clearing Sequence272................................................................................................................................................................
Sci Status Register 2273................................................................................................................................................................
Sci Data Register274................................................................................................................................................................
Sci Baud Rate Register275................................................................................................................................................................
Sci Baud Rate Selection276................................................................................................................................................................
Sci Baud Rate Selection Examples277................................................................................................................................................................
Section 16. Serial Peripheral Interface Module (spi)279................................................................................................................................................................
Pin Name Conventions And I/o Register Addresses281................................................................................................................................................................
Spi Module Block Diagram282................................................................................................................................................................
Master Mode283................................................................................................................................................................
Slave Mode284................................................................................................................................................................
Transmission Formats285................................................................................................................................................................
Transmission Format When Cpha = 0286................................................................................................................................................................
Transmission Format (cpha = 0)287................................................................................................................................................................
Transmission Format When Cpha = 1288................................................................................................................................................................
Transmission Initiation Latency289................................................................................................................................................................
Transmission Start Delay (master)290................................................................................................................................................................
Queuing Transmission Data291................................................................................................................................................................
Error Conditions292................................................................................................................................................................
Missed Read Of Overflow Condition293................................................................................................................................................................
Mode Fault Error294................................................................................................................................................................
Spi Interrupt Request Generation297................................................................................................................................................................
Resetting The Spi298................................................................................................................................................................
Spi During Break Interrupts300................................................................................................................................................................
Miso (master In/slave Out)301................................................................................................................................................................
Spsck (serial Clock)302................................................................................................................................................................
Cgnd (clock Ground)303................................................................................................................................................................
Spi Status And Control Register306................................................................................................................................................................
Spi Master Baud Rate Selection308................................................................................................................................................................
Spi Data Register309................................................................................................................................................................
Section 17. Input/output (i/o) Ports311................................................................................................................................................................
Port Control Register Bits Summary314................................................................................................................................................................
Port A Data Register (pta)316................................................................................................................................................................
Port A I/o Circuit317................................................................................................................................................................
Port B Data Register (ptb)318................................................................................................................................................................
Data Direction Register B (ddrb)319................................................................................................................................................................
Port C Data Register (ptc)320................................................................................................................................................................
Data Direction Register C (ddrc)321................................................................................................................................................................
Port C I/o Circuit322................................................................................................................................................................
Port D Data Register (ptd)323................................................................................................................................................................
Data Direction Register D (ddrd)324................................................................................................................................................................
Port D Input Pullup Enable Register (ptdpue)325................................................................................................................................................................
Port E Data Register (pte)326................................................................................................................................................................
Data Direction Register E (ddre)328................................................................................................................................................................
Port F Data Register (ptf)329................................................................................................................................................................
Data Direction Register F (ddrf)330................................................................................................................................................................
Port F I/o Circuit331................................................................................................................................................................
Port F Input Pullup Enable Register (ptfpue)332................................................................................................................................................................
Data Direction Register G (ddrg)333................................................................................................................................................................
Port G I/o Circuit334................................................................................................................................................................
Port H335................................................................................................................................................................
Data Direction Register H (ddrh)336................................................................................................................................................................
Port H Pin Functions337................................................................................................................................................................
Section 18. External Interrupt (irq)339................................................................................................................................................................
Irq Module Block Diagram341................................................................................................................................................................
Irq Pin342................................................................................................................................................................
Irq Status And Control Register (iscr)343................................................................................................................................................................
Irq Module During Break Interrupts344................................................................................................................................................................
Section 19. Keyboard Interrupt Module (kbi)345................................................................................................................................................................
Keyboard Initialization349................................................................................................................................................................
Keyboard Status And Control Register (kbscr)350................................................................................................................................................................
Keyboard Interrupt Enable Register351................................................................................................................................................................
Keyboard Module During Break Interrupts352................................................................................................................................................................
Section 20. Computer Operating Properly (cop)353................................................................................................................................................................
Internal Reset356................................................................................................................................................................
Cop Control Register357................................................................................................................................................................
Section 21. Low-voltage Inhibit (lvi)359................................................................................................................................................................
Polled Lvi Operation361................................................................................................................................................................
Lvi Status Register (lvisr)362................................................................................................................................................................
Section 22. Break Module (brk)365................................................................................................................................................................
Break Module Block Diagram367................................................................................................................................................................
Flag Protection During Break Interrupts368................................................................................................................................................................
Break Address Registers370................................................................................................................................................................
Sim Break Status Register (sbsr)371................................................................................................................................................................
Section 23. Electrical Specifications373................................................................................................................................................................
Absolute Maximum Ratings374................................................................................................................................................................
Functional Operating Range375................................................................................................................................................................
V Dc Electrical Characteristics376................................................................................................................................................................
Eeprom And Memory Characteristics377................................................................................................................................................................
V Control Timing378................................................................................................................................................................
Adc Characteristics379................................................................................................................................................................
Spi Characteristics380................................................................................................................................................................
Spi Master Timing381................................................................................................................................................................
Spi Slave Timing382................................................................................................................................................................
Clock Generation Module Characteristics383................................................................................................................................................................
Cgm Acquisition/lock Time Information384................................................................................................................................................................
Flash Memory Characteristics385................................................................................................................................................................
Section 24. Mechanical Specifications387................................................................................................................................................................
Pin Plastic Quad Flat Pack (qfp)388................................................................................................................................................................
Section 25. Ordering Information389................................................................................................................................................................

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