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Computer Operating Properly (COP)
20.3 Functional Description
CGMXCLK
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
NOTE:
Technical Data
354
Figure 20-1
shows the structure of the COP module.
12-BIT COP PRESCALER
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 20-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in configuration register 1. With a 2
overflow option, a 4.9152MHz crystal gives a COP timeout period of
53.3ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Computer Operating Properly (COP)
RESET CIRCUIT
RESET STATUS REGISTER
18
4
13
4
– 2
or 2
– 2
18
4
– 2
CGMXCLK cycle
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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