Input/Output (I/O) Ports
Table 17-1. Port Control Register Bits Summary (Sheet 1 of 2)
Port
Bit
0
1
2
3
A
4
5
6
7
0
1
2
3
B
4
5
6
7
0
1
2
C
3
4
5
0
1
2
3
D
4
5
6
7
Technical Data
314
DDR
Module
DDRA0
DDRA1
DDRA2
DDRA3
—
DDRA4
DDRA5
DDRA6
DDRA7
DDRB0
DDRB1
DDRB2
DDRB3
ADC
DDRB4
DDRB5
DDRB6
DDRB7
DDRC0
—
DDRC1
DDRC2
—
DDRC3
DDRC4
—
DDRC5
DDRD0
DDRD1
—
DDRD2
DDRD3
DDRD4
TIMB
DDRD5
—
DDRD6
TIMA
DDRD7
—
Input/Output (I/O) Ports
Module Control
Register
Control Bit
—
—
ADSCR
ADCH[4:0]
$0038
—
—
DDRC
MCLKEN
$0006
—
—
—
—
TBSC
PS[2:0]
$0040
—
—
TASC
PS[2:0]
$0020
—
—
Pin
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD6
PTB7/ATD7
PTC0
PTC1
PTC2/MCLK
PTC3
PTC4
PTC5
PTD0
PTD1
PTD2
PTD3
PTD4/TBCLK
PTD5
PTD6/TACLK
PTD7
MC68HC908AB32
Rev. 1.0
—
MOTOROLA