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Break Module (BRK)
22.4.1 Flag Protection During Break Interrupts
22.4.2 CPU During Break Interrupts
22.4.3 PIT, TIMA, and TIMB During Break Interrupts
22.4.4 COP During Break Interrupts
22.5 Low-Power Modes
22.5.1 Wait Mode
Technical Data
368
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.
The CPU starts a break interrupt by:
•
Loading the instruction register with the SWI instruction
•
Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops all timer counters.
The COP is disabled during a break interrupt when V
the RST pin.
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see
Section 8. System Integration Module
SBSW bit by writing logic 0 to it.
Break Module (BRK)
is present on
TST
(SIM)). Clear the
MC68HC908AB32
Rev. 1.0
—
MOTOROLA
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